How ya gonna’ control that DDR4 SDRAM next year? The 28nm answer.

Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with DDR3 and DDR3L SDRAM devices as well. The same test chip also included an all-digital mobile SDRAM PHY capable of DDR-1600 and DDR-1833 DDR3 data rates and full-speed LPDDR2 SDRAM data rates as well. In addition, the test chip included a copy of the Cadence DDR4 SDRAM controller, so that too is now silicon proven.

Although the JEDEC DDR4 SDRAM specification is still in draft form, it’s expected in final form later this year. Production SDRAM devices based on this standard will follow shortly after finalizing the spec, as evidenced by early prototype announcements from Micron and Samsung. You can expect to see the first products based on DDR4 memory to begin appearing next year.

For more information on DDR4, see:

The DDR4 SDRAM spec and SoC design. What do we know now?

and

Memory to processors: ‘Without me, you’re nothing.’ DDR4 is on the way.

For more information on the Cadence announcement, see “Cadence Announces Industry’s First DDR4 Design IP Solutions Are Now Proven in 28nm Silicon.”

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in DDR, DDR3, DDR4, DRAM, LPDDR2, SDRAM and tagged , , , , , , , . Bookmark the permalink.

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