Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
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Recent Posts
- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
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Category Archives: DRAM
Future Memory: The MemCon Panel. What comes after NAND Flash and DRAM?
Just announced, there’s a pre-lunch panel at MemCon covering future memories. There are several new memory technologies that would usurp the thrones from DRAM and NAND Flash memory. Will any succeed? Come and hear the panel to find out. Jim … Continue reading
Posted in DRAM, Flash, MRAM, NAND
Tagged DRAM, Flash memory, NAND Flash, Santa Clara Convention Center
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How ya gonna’ control that DDR4 SDRAM next year? The 28nm answer.
Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, SDRAM
Tagged DDR3 SDRAM, DDR4 SDRAM, JEDEC, Micron, Micron Technology, Samsung, technology, TSMC
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Want to know why SK hynix is placing its bets on three different alternatives to DRAM and Flash?
Last week at the Flash Memory Summit, Dr. Sung Wook Park spoke about memory. No surprise there, but there were several surprises in Park’s presentation. The first surprise popped up in the slide immediately following the keynote presentation’s title slide: … Continue reading
Memcon is filling up. Register now to be sure you get a ticket. It’s free. September 18. Silicon Valley
The Flash Memory Summit took place this week and registration for next month’s Memcon in Silicon Valley suddenly took a big uptick. I’d like to suggest that if you want to be certain to attend Memcon next month, you might … Continue reading
Friday Video: A personal invitation to Memcon from Sanjay Srivastava
Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading
Can you make money selling DRAM? The Memory Guy says “yes,” but perhaps not all of the time
Jim Handy, The Memory Guy, has decided to become a Mythbuster with respect to the meme: “You cannot make a profit in the DRAM manufacturing business.” He just published a blog post titled “Is DRAM Really a Profitless Business?” This … Continue reading
Initial Hybrid Memory Cube short-reach interconnect specification issued to Consortium adopters
The Hybrid Memory Cube Consortium (HMCC), now supported by the three top DRAM vendors (Samsung, SK hynix, and Micron), has just issued an initial draft specification for the Hybrid Memory Cube’s “short-reach interconnection across physical layers”—in other words, the short-reach … Continue reading
Posted in 3D, DRAM, HMC, Hybrid Memory Cube, Hynix, Micron, Samsung
Tagged Hybrid Memory Cube, IBM, Micron, MicronTechnology, PHY, Samsung, SerDes
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Test your system design for DDR4 JEDEC compliance with this $4500 ‘Scope add-on
Agilent has just announced a compliance test application for DDR4 SDRAM system designs. The $4500 Agilent N6462A DDR4 test application accelerates bring-up and debugging of DDR4 SDRAM-based systems by automating a bevy of physical-layer I/O testing with the company’s 9000 … Continue reading
Posted in DDR, DDR4, DRAM, SDRAM
Tagged Agilent, Agilent Technologies, DDR4 SDRAM, JEDEC, Memcon, Oscilloscope
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Save the date: JEDEC DDR4 Workshop, Santa Clara, CA. October 30-31
JEDEC is sponsoring a 2-day DDR4 workshop that should interest anyone planning on using DDR4 SDRAM in next-generation designs. Day 1: DDR4 vs DDR3: Comparison Matrix Why migrate to DDR4 Power-on, initialization, and training Read/Write and refresh operation review Day … Continue reading
See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video
This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, LPDDR3, Wide I/O
Tagged DDR3 SDRAM, DDR4 SDRAM, DRAM, SDRAM
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How many DRAMs does it take to populate a supercomputer? 746,496 plus a lot of hot water for cooling
Jim Handy, The Memory Guy, posted a short blog about the 3-petaFLOP (peak) SuperMUC supercomputer at the Leibniz Supercomputing Centre on the outskirts of Munich, Germany. (The “MUC” in SuperMUC is the 3-letter code for the Munich airport. Now that’s … Continue reading
Who do you want to see at Memcon?
As the emcee for the Memcon event on September 18, I’ve been given the opportunity to personally invite a few, select exhibitors to the show and to cut them a very sweet deal. To do that, I’d like to know … Continue reading
Micron announces volume production of PCM/DRAM multichip packaged memory
Totally not expecting this. Today Micron announced high-volume availability of a multichip, packaged memory device that incorporates a 1Gbit PCM (Phase-Change Memory) and a 512Mbit LPDDR2 SDRAM. The PCM die is built with 45nm process technology. The multichip-packaged memory is … Continue reading
Want another opinion about the Hybrid Memory Cube? Michael Feldman of HPCwire.com weighs in
Michael Feldman over at HPCwire.com has just published his own analysis of the Hybrid Memory Cube (HMC), which I’ve covered extensively in the EDA360 Insider and the Denali Memory Report (see below). Feldman reiterates many of the same points I’ve … Continue reading
Posted in DDR, DRAM, HMC, Hybrid Memory Cube, Micron
Tagged DRAM, Dynamic random-access memory, Flash memory, HMC, Michael Feldman, Micron
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ARM, HP, and SK hynix join Hybrid Memory Cube Consortium (HMCC). First spec due by end of year
Add ARM, HP, and SK hynix to the growing list of companies in the Hybrid Memory Cube Consortium (HMCC). The three new members join the original founding companies, Micron and Samsung, along with Altera, IBM, Microsoft, Open-Silicon, and Xilinx plus … Continue reading
Second Samsung memory video just as amusing as the first
Yesterday, I posted a blog entry about an amusing Samsung memory video aimed at memory consumers with a fanciful supervillian named Fiona Freeze who was responsible for causing device freezups. Today, I present the Samsung Memory Battery Brutus video. Battery … Continue reading
Samsung’s 20nm-class DDR3 SDRAM runs on 1.35V, saves 2/3 of the power used by 50nm-class, 1.5V SDRAM
Not all DDR3 SDRAM is created equal. That’s the message Samsung is spreading lately by talking about its 20nm-class DDR3 SDRAM. The company is using 1.5V, 50nm-class DDR3 SDRAM as a benchmark and says that a server loaded with 96Mbytes … Continue reading
So just how big is the semiconductor memory market? $50 billion? $60 billion?
Yesterday, Jeremy Wagstaff, Chief Technology Correspondent for Reuters in Asia, published an article on wannabe non-volatile memory technologies such as MRAM and Memristors or ReRAM (See “Pushing the PRAM: when chips just can’t get any smaller”). The lure is a … Continue reading
Will SSDs be the first big market for 3D NAND Flash memories?
I’ve been meaning to write about a comment regarding NAND Flash memory and SSDs written by Thomas McCormick in LinkedIn’s Solid State Storage Group and this seems like the perfect time. McCormick is an Integrated Hardware/Software Product Development Leader at … Continue reading
Posted in 3D, DDR, DRAM, Flash, Memristor, MRAM, NAND, SSD, Storage
Tagged DRAM, Flash, Flash memory, memristor, MRAM, NAND Flash, Solid-state drive, SSD
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It’s Official: Microsoft joins 3D Hybrid Memory Cube Consortium with Micron, Samsung, Altera, IBM, Open-Silicon, and Xilinx
Last week, the Hybrid Memory Cube Consortium announced that Microsoft had joined Micron, Samsung, Altera, IBM, Open-Silicon, and Xilinx in the development of high-performance 3D SDRAM subsystems based on the Hybrid Memory Cube. For more information on the Hybrid Memory … Continue reading
Posted in 3D, DRAM, HMC, Hybrid Memory Cube
Tagged Altera, Hybrid Memory Cube, IBM, Micron, Microsoft, Open-Silicon, Samsung, Xilinx
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Micron samples DDR4 module at 2400Mtransfers/sec. Production pegged in 2013
Micron has begun sampling a DDR4 SDRAM module, which the company has said will lead the way to DDR4 availability in production equipment starting in 2013. The memory chips on the Micron DDR4 module are 30nm, 4Gbit, x8 parts operating … Continue reading
Posted in DDR4, DRAM, JEDEC, SDRAM
Tagged DDR4 SDRAM, JEDEC, Micron, Micron Technology, Nanya, SDRAM, SO-DIMM
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Multicore, the Memory Wall, and Numerical Compression—FREE Webcast now available
Last month I posted a review of Al Wegener’s terrific IEEE Computer Society presentation at Cadence titled “Multicore, the Memory Wall, and Numerical Compression.” (See “Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? … Continue reading
Posted in DRAM, SDRAM, SRAM
Tagged IEEE Computer Society, memory, Multi-core processor, Samplify Systems, Wegener
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Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products… we need low-cost 3D IC assembly”
Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including … Continue reading
Posted in 3D, DRAM, SDRAM, Wide I/O
Tagged Computer History Museum, GSM, Holy Grail, JEDEC, Qualcomm
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Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?
Multicore SoC and processor designs were our solution to the death of Dennard Scaling when IC process geometries dropped below 90nm, when processor speeds hit 3GHz, and when processor power consumption went off the charts. Since 2004, we’ve transformed Moore’s … Continue reading
Posted in 3D, DDR, DDR3, DDR4, DRAM, Flash, PCIe, Wide I/O
Tagged DDR SDRAM, Graphics processing unit, System-on-a-chip, X86
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A possible roadmap for Wide I/O that leads to 2Tbps of SDRAM memory bandwidth—per device
Cadence Product Marketing Director Marc Greenberg—one of the speakers at last week’s EDPS conference held in Monterey, California—spoke about why the Wide I/O SDRAM is probably the “killer app” that unleashes 3D IC assembly into the mainstream. Richard Goering has … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, SDRAM, Wide I/O
Tagged DDR SDRAM, Double data rate, JEDEC, Memory bandwidth, Wide I/O
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4th International Memory Workshop in Milan tackles all things non-volatile with respect to semiconductor memory. May 20-23
You will need to travel to Milan, Italy to attend the 4-day intensive event devoted to non-volatile memory, which seems to be the exclusive topic for the 4th International Memory Workshop Symposia on VLSI Technology and Circuits covers latest STT-MRAM … Continue reading
Free Webinar on essential memory and storage verification IP: DDR3/4, LRDIMM, 12Gbps SAS, NVMe, Ethernet. April 10.
Verification IP (VIP) is an essential component of the development process for all ICs and systems and now you have the chance to listen to a free April 10 Webinar on applying that essential component in memory and storage applications. … Continue reading
Want some additional details about the Micron Hybrid Memory Cube?
This week at Design West (the conference previously known as the Embedded Systems Conference), I had a chance to speak with Mike Black from Micron about the Hybrid Memory Cube (HMC), a 3D DRAM assembly aimed at high-performance computing. The … Continue reading
Posted in 3D, DRAM, HMC, Hybrid Memory Cube
Tagged Altera, FPGA, HMC, Hybrid Memory Cube, IBM
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ISQED: Who and what will win the Universal Memory Derby?
Professor Cristophe Muller of Aix-Marseille University gave an excellent overview of non-volatile semiconductor memory as the third ISQED keynote this week. It’s a very good overview of today’s landscape and well worth discussing in a wider forum like this blog. … Continue reading
Want to avoid losing more than half of your SDRAM’s bandwidth? The right SDRAM controller configuration can help prevent the loss. Just ask Vivante.
Graphics processors (GPUs) suck bits out of SDRAMs the way vampires do what comes naturally to them in the immensely popular Twilight book series by Stephenie Meyer. In other words, GPUs need all the memory bandwidth they can get and … Continue reading
Agilent: Memory technology has hit a wall due to physics limitations and that has implications for your designs
Last week, Agilent ran a seminar in Milpitas, California. The first of three subseminars was about memory technology with an excellent overview of the state of memory technology today. It was presented by Gordon Getty, an Agilent Application Engineer based … Continue reading
DRAMeXchange opines on six major DRAM and NAND Flash trends for 2012-2015. What do you think?
The DRAMeXchange http://www.dramexchange.com/ keeps a very close watch on the spot and contract prices for all forms of semiconductor memory including DRAM and NAND Flash devices. The group also keeps an eye on trends that may affect pricing. A couple … Continue reading
Posted in 3D, DDR3, DDR4, DRAM, Flash, HDD, LPDDR2, LPDDR3, Memcon, ONFI, Toggle
Tagged DDR3 SDRAM, Flash, Flash memory, NAND Flash, PCI Express, Ultrabook
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More DDR4, DDR3, and 3D IC technical details from ISSCC, courtesy of memory analyst and expert Jim Handy
Semiconductor memory analyst and expert Jim Handy has just published an overview of some memory papers given at last week’s ISSCC. Handy’s article on the ElectroIQ web site supplements some of the previous Denali Memory Report blog entries published earlier … Continue reading
Quickly Noted: EETimes on the challenges of testing semiconductor memory for mobile applications. Is testing really a 3D IC “stopper”?
Janine Love at EETimes interviewed Cecil Ho, President of CST (Simmtester.com)—a memory tester vendor, about issues surrounding the testing of semiconductor memory that’s optimized for and aimed at mobile applications. In these applications board real estate and physical volume are … Continue reading
Could the memory business be a major driver for the semiconductor foundry business? MonolithIC 3D’s Deepak Sekar says “Yes!”
Deepak Sekar, Chief Scientist at MonolithIC 3D, has just published a provocative blog with big implications for both the semiconductor memory and foundry businesses. His premise is that even though Samsung has “only” about 7% of the semiconductor foundry business, … Continue reading
LeCroy introduces DDR4 Bus and Timing Analyzer at DesignCon 2012
LeCroy’s Kibra 480 DDR bus and timing analyzer now lets you analyze bust traffic on DDR4 interfaces at the board and connector level. It is an evolution from the company’s earlier Kibra 380 DDR3 bus and timing analyzer. (See “How … Continue reading
JEDEC to hold free server memory forum in Shenzen, March 1
Anyone involved in the development and use of server memory will want to consider the free server memory forum that JEDEC will be holding in Shenzen, China on March 1. Current agenda: Server memory roadmaps and trends DDR4 as enterprise … Continue reading
Elpida prototypes 50nm, 64Mbit, 10nsec Resistive RAM (ReRAM). 30nm production slated for 2013
Elpida, the world’s third largest DRAM manufacturer, just announced successful development of a 64Mbit resistive RAM (ReRAM) prototype chip using a 50nm process technology. Two key specs for this prototype are a 10nsec write speed, similar to DRAM and orders … Continue reading
JEDEC Mobile Memory Summit: The pace quickens and memory standards must keep up
By Scott Jacobson CES hosted the JEDEC Mobile Memory Summit on January 12th to review the current state of the market for mobile semiconductor memory and to discuss future trends. It was a full day review of current mobile device … Continue reading
Posted in DRAM, eMMC, Flash, JEDEC, NAND, UFS
Tagged Feature Phone, Flash, JEDEC, LPDDR3 SDRAM, Mobile, MultiMediaCard, Smartphone, Universal Flash Storage
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Microprocessor Report names Micron Hybrid Memory Cube as “Best Microprocessor Technology” of the year
This week, Microprocessor Report selected the Micron Hybrid Memory Cube (HMC) as the “Best Microprocessor Technology” of 2011. Why? As Tom Halfhill writes: “Memory cubes promise greater density, lower latency, higher bandwidth, and better power efficiency per bit compared with … Continue reading
Samsung packages 4Gbytes of NAND Flash with LPDDR2 DRAM for smartphone and other embedded applications
Samsung has announced that it has started volume production of a combined NAND Flash/DRAM “embedded multichip module” (eMCP). The module combines 30nm-class LPDDR2 DRAM chips (packaged capacities of 256, 512, or 768 Mbytes) with 4Gbytes of 20nm-class NAND Flash in … Continue reading
Is MRAM ramping up to the big time?
Today, MRAM (magnetic RAM) supplier Everspin announced that it expects to close out FY 2011 with a shipment volume that exceeds that of 2010 by more than a factor of three. MRAM combines the thin-film magnetics initially developed for the … Continue reading
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