Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
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Recent Posts
- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
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Tag Archives: DDR4 SDRAM
IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
IDT has announced a small but essential component for the development of advanced DDR4 DIMMs: the 4RCD0124 DDR4 register. A device of this type is required for building DDR4 DIMMs to provide registered buffering. In addition, the 4RCD0124 DDR4 register … Continue reading
How ya gonna’ control that DDR4 SDRAM next year? The 28nm answer.
Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, SDRAM
Tagged DDR3 SDRAM, DDR4 SDRAM, JEDEC, Micron, Micron Technology, Samsung, technology, TSMC
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Test your system design for DDR4 JEDEC compliance with this $4500 ‘Scope add-on
Agilent has just announced a compliance test application for DDR4 SDRAM system designs. The $4500 Agilent N6462A DDR4 test application accelerates bring-up and debugging of DDR4 SDRAM-based systems by automating a bevy of physical-layer I/O testing with the company’s 9000 … Continue reading
Posted in DDR, DDR4, DRAM, SDRAM
Tagged Agilent, Agilent Technologies, DDR4 SDRAM, JEDEC, Memcon, Oscilloscope
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Save the date: JEDEC DDR4 Workshop, Santa Clara, CA. October 30-31
JEDEC is sponsoring a 2-day DDR4 workshop that should interest anyone planning on using DDR4 SDRAM in next-generation designs. Day 1: DDR4 vs DDR3: Comparison Matrix Why migrate to DDR4 Power-on, initialization, and training Read/Write and refresh operation review Day … Continue reading
See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video
This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, LPDDR3, Wide I/O
Tagged DDR3 SDRAM, DDR4 SDRAM, DRAM, SDRAM
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DFI 3.1 spec adds DDR4 and LPDDR3 coverage for speed and low-power benefits
Earlier this month, JEDEC published the LPDDR3 specification for the next generation of low-power SDRAM that will be used in mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks. The LPDDR3 … Continue reading
Micron samples DDR4 module at 2400Mtransfers/sec. Production pegged in 2013
Micron has begun sampling a DDR4 SDRAM module, which the company has said will lead the way to DDR4 availability in production equipment starting in 2013. The memory chips on the Micron DDR4 module are 30nm, 4Gbit, x8 parts operating … Continue reading
Posted in DDR4, DRAM, JEDEC, SDRAM
Tagged DDR4 SDRAM, JEDEC, Micron, Micron Technology, Nanya, SDRAM, SO-DIMM
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DDR4 DIMM and SO-DIMM interposer modules work with Agilent logic analyzers
FuturePlus Systems has announced a pair of DDR4 SDRAM interposer modules compatible with Agilent logic analyzers to aid in hardware debugging of DDR4-based memory systems. The FS2501 interposer module works with DDR4 DIMMs at transfer rates to 2133Mtransfer/sec and the … Continue reading
Posted in DDR4, SDRAM
Tagged Agilent, Agilent Technologies, DDR4 SDRAM, DIMM, Logic analyzer, SO-DIMM
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More DDR4, DDR3, and 3D IC technical details from ISSCC, courtesy of memory analyst and expert Jim Handy
Semiconductor memory analyst and expert Jim Handy has just published an overview of some memory papers given at last week’s ISSCC. Handy’s article on the ElectroIQ web site supplements some of the previous Denali Memory Report blog entries published earlier … Continue reading
LeCroy introduces DDR4 Bus and Timing Analyzer at DesignCon 2012
LeCroy’s Kibra 480 DDR bus and timing analyzer now lets you analyze bust traffic on DDR4 interfaces at the board and connector level. It is an evolution from the company’s earlier Kibra 380 DDR3 bus and timing analyzer. (See “How … Continue reading
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