Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
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Recent Posts
- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
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- DDR
- DDR3
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Meta
Category Archives: DDR3
How ya gonna’ control that DDR4 SDRAM next year? The 28nm answer.
Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, SDRAM
Tagged DDR3 SDRAM, DDR4 SDRAM, JEDEC, Micron, Micron Technology, Samsung, technology, TSMC
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Friday Video: A personal invitation to Memcon from Sanjay Srivastava
Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading
See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video
This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, LPDDR3, Wide I/O
Tagged DDR3 SDRAM, DDR4 SDRAM, DRAM, SDRAM
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How many DRAMs does it take to populate a supercomputer? 746,496 plus a lot of hot water for cooling
Jim Handy, The Memory Guy, posted a short blog about the 3-petaFLOP (peak) SuperMUC supercomputer at the Leibniz Supercomputing Centre on the outskirts of Munich, Germany. (The “MUC” in SuperMUC is the 3-letter code for the Munich airport. Now that’s … Continue reading
Samsung’s 20nm-class DDR3 SDRAM runs on 1.35V, saves 2/3 of the power used by 50nm-class, 1.5V SDRAM
Not all DDR3 SDRAM is created equal. That’s the message Samsung is spreading lately by talking about its 20nm-class DDR3 SDRAM. The company is using 1.5V, 50nm-class DDR3 SDRAM as a benchmark and says that a server loaded with 96Mbytes … Continue reading
Designing circuit boards with DDR3? Full-day, hands-on tutorial in Europe shows you how. Munich, May 14
System designs employing DDR3 SDRAMs present many new pcb design challenges compared to DDR2. DDR3 clock, address, and control lines employ a new fly-by topology; setup and hold times need to be just right because there are reduced timing margins … Continue reading
Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?
Multicore SoC and processor designs were our solution to the death of Dennard Scaling when IC process geometries dropped below 90nm, when processor speeds hit 3GHz, and when processor power consumption went off the charts. Since 2004, we’ve transformed Moore’s … Continue reading
Posted in 3D, DDR, DDR3, DDR4, DRAM, Flash, PCIe, Wide I/O
Tagged DDR SDRAM, Graphics processing unit, System-on-a-chip, X86
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A possible roadmap for Wide I/O that leads to 2Tbps of SDRAM memory bandwidth—per device
Cadence Product Marketing Director Marc Greenberg—one of the speakers at last week’s EDPS conference held in Monterey, California—spoke about why the Wide I/O SDRAM is probably the “killer app” that unleashes 3D IC assembly into the mainstream. Richard Goering has … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, SDRAM, Wide I/O
Tagged DDR SDRAM, Double data rate, JEDEC, Memory bandwidth, Wide I/O
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Free Webinar on essential memory and storage verification IP: DDR3/4, LRDIMM, 12Gbps SAS, NVMe, Ethernet. April 10.
Verification IP (VIP) is an essential component of the development process for all ICs and systems and now you have the chance to listen to a free April 10 Webinar on applying that essential component in memory and storage applications. … Continue reading
Where does LPDDR3 SDRAM fit in the low-power memory universe? How about Wide I/O SDRAM?
Marc Greenberg, Director of Product Marketing in the Cadence SoC Realization Design IP Group, just sent me some slides in connection with the recent introduction of the Cadence design and verification IP portfolio for LPDDR3 low-power SDRAM. I’ve already written … Continue reading
Agilent: Memory technology has hit a wall due to physics limitations and that has implications for your designs
Last week, Agilent ran a seminar in Milpitas, California. The first of three subseminars was about memory technology with an excellent overview of the state of memory technology today. It was presented by Gordon Getty, an Agilent Application Engineer based … Continue reading
DRAMeXchange opines on six major DRAM and NAND Flash trends for 2012-2015. What do you think?
The DRAMeXchange http://www.dramexchange.com/ keeps a very close watch on the spot and contract prices for all forms of semiconductor memory including DRAM and NAND Flash devices. The group also keeps an eye on trends that may affect pricing. A couple … Continue reading
Posted in 3D, DDR3, DDR4, DRAM, Flash, HDD, LPDDR2, LPDDR3, Memcon, ONFI, Toggle
Tagged DDR3 SDRAM, Flash, Flash memory, NAND Flash, PCI Express, Ultrabook
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Get the specifics of designing DDR3 SDRAM into a pcb with timing closure and good signal integrity
Next week at CDNLive!, EMA Design Automation will give a presentation on designing DDR3 SDRAM into a pcb with attention given to the signal integrity issues and timing closure. This session is one of seven pcb-specific sessions at CDNLive! on … Continue reading
More DDR4, DDR3, and 3D IC technical details from ISSCC, courtesy of memory analyst and expert Jim Handy
Semiconductor memory analyst and expert Jim Handy has just published an overview of some memory papers given at last week’s ISSCC. Handy’s article on the ElectroIQ web site supplements some of the previous Denali Memory Report blog entries published earlier … Continue reading
LeCroy introduces DDR4 Bus and Timing Analyzer at DesignCon 2012
LeCroy’s Kibra 480 DDR bus and timing analyzer now lets you analyze bust traffic on DDR4 interfaces at the board and connector level. It is an evolution from the company’s earlier Kibra 380 DDR3 bus and timing analyzer. (See “How … Continue reading
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