Category Archives: LPDDR2

How ya gonna’ control that DDR4 SDRAM next year? The 28nm answer.

Posted on September 4, 2012 by sleibson2

Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with … Continue reading →

Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, SDRAM | Tagged , , , , , , , | Leave a comment

Friday Video: A personal invitation to Memcon from Sanjay Srivastava

Posted on August 17, 2012 by sleibson2

Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading →

Posted in DDR3, DDR4, DRAM, Flash, HMC, Hybrid Memory Cube, JEDEC, LPDDR2, LPDDR3, LPDDR4, Memcon, MRAM, mSATA, NAND, NOR, NVM Express, NVMe, ONFI, PCIe, Samsung, SAS, SATA, SD, SDRAM | Tagged , , , | Leave a comment

See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video

Posted on August 2, 2012 by sleibson2

This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading →

Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, LPDDR3, Wide I/O | Tagged , , , | Leave a comment

Want more details about the new Micron 1Gbit Phase-Change Memory / 512Mbit SDRAM device? Here are several

Posted on July 19, 2012 by sleibson2

Yesterday, Micron announced volume production of a new memory device containing one 1Gbit PCM (phase-change memory) die and one 512Mbit LPDDR2 SDRAM die. This morning, I had a conversation about this new device with Philippe Berge—Senior Director of the NOR, … Continue reading →

Posted in DDR, Flash, LPDDR2, Micron, NOR, PCM, Storage | Tagged , , , , , , , | Leave a comment

Micron announces volume production of PCM/DRAM multichip packaged memory

Posted on July 17, 2012 by sleibson2

Totally not expecting this. Today Micron announced high-volume availability of a multichip, packaged memory device that incorporates a 1Gbit PCM (Phase-Change Memory) and a 512Mbit LPDDR2 SDRAM. The PCM die is built with 45nm process technology. The multichip-packaged memory is … Continue reading →

Posted in DRAM, LPDDR2, Micron, PCM, SDRAM | Tagged , , , | 1 Comment

Want a quick and dirty overview of the new JEDEC LPDDR3 spec? EETimes serves it up

Posted on June 13, 2012 by sleibson2

Kristin Lewotsky has just published an LPDDR3 SDRAM interview with Huong Vuong, Chairman of the JEDEC JC-42.6 Subcommittee for Low Power Memories. Here are the salient points from the interview, in my opinion: The purpose of LPDDR3 is to increase … Continue reading →

Posted in LPDDR2, LPDDR3, LPDDR3E, LPDDR4, SDRAM | Tagged , , , , , , | Leave a comment

Semiconductor memory plays a large role in smartphone design says Matti Floman of Nokia

Posted on May 16, 2012 by sleibson2

“There’s no real difference between PCs and mobile phones today,” said Matti Floman from Nokia who gave the first keynote speech at last week’s JEDEC Mobile Forum. There is no difference in the types of applications run; there’s no difference … Continue reading →

Posted in 3D, DDR, LPDDR2, Memristor, MRAM, SDRAM, Storage, UFS | Tagged , , , , , | Leave a comment

Where does LPDDR3 SDRAM fit in the low-power memory universe? How about Wide I/O SDRAM?

Posted on March 22, 2012 by sleibson2

Marc Greenberg, Director of Product Marketing in the Cadence SoC Realization Design IP Group, just sent me some slides in connection with the recent introduction of the Cadence design and verification IP portfolio for LPDDR3 low-power SDRAM. I’ve already written … Continue reading →

Posted in DDR, DDR3, LPDDR, LPDDR2, LPDDR3, SDRAM, Wide I/O | Tagged , | 2 Comments

Upgrading your mobile or low-power SoC to LPDDR3? Got the right IP? You’ll need it to get maximum performance at minimum power

Posted on March 21, 2012 by sleibson2

LPDDR3 is JEDEC’s next click on the low-power LPDDR SDRAM standard for mobile, portable, and other low-power devices. According to the JEDEC Web site, the LPDDR3 standard is still in development but the technical specs of the early devices announced … Continue reading →

Posted in DDR, JEDEC, LPDDR, LPDDR2, LPDDR3, SDRAM | Tagged , , , | 1 Comment

Agilent: Memory technology has hit a wall due to physics limitations and that has implications for your designs

Posted on March 12, 2012 by sleibson2

Last week, Agilent ran a seminar in Milpitas, California. The first of three subseminars was about memory technology with an excellent overview of the state of memory technology today. It was presented by Gordon Getty, an Agilent Application Engineer based … Continue reading →

Posted in 3D, DDR3, DDR4, DRAM, eMMC, Flash, LPDDR2, LPDDR3, NAND, NOR, QDR, SD, SDRAM, Storage | Tagged , , , , , , , , , , , , | 1 Comment

DRAMeXchange opines on six major DRAM and NAND Flash trends for 2012-2015. What do you think?

Posted on March 9, 2012 by sleibson2

The DRAMeXchange http://www.dramexchange.com/ keeps a very close watch on the spot and contract prices for all forms of semiconductor memory including DRAM and NAND Flash devices. The group also keeps an eye on trends that may affect pricing. A couple … Continue reading →

Posted in 3D, DDR3, DDR4, DRAM, Flash, HDD, LPDDR2, LPDDR3, Memcon, ONFI, Toggle | Tagged , , , , , | Leave a comment

Samsung packages 4Gbytes of NAND Flash with LPDDR2 DRAM for smartphone and other embedded applications

Posted on January 20, 2012 by sleibson2

Samsung has announced that it has started volume production of a combined NAND Flash/DRAM “embedded multichip module” (eMCP). The module combines 30nm-class LPDDR2 DRAM chips (packaged capacities of 256, 512, or 768 Mbytes) with 4Gbytes of 20nm-class NAND Flash in … Continue reading →

Posted in DRAM, LPDDR2, NAND | Tagged | Leave a comment

Big week for Wide I/O: JEDEC publishes spec while Elpida ships sample 4Gbit parts

Posted on January 5, 2012 by sleibson2

Wide I/O jumped closer to being a reality this week with two major announcements. On December 28th, Elpida announced that they were making sample shipments of 4Gbit Wide-IO. (See “Let’s start the new year with a bang! Elpida ships 4Gbit … Continue reading →

Posted in JEDEC, LPDDR2, SDRAM, Wide I/O | Tagged , , , , , , | Leave a comment

Let’s start the new year with a bang! Elpida ships 4Gbit Wide I/O and LPDDR3 SDRAM samples

Posted on January 5, 2012 by sleibson2

Two DRAM categories that will shake up mobile product design this year are Wide I/O and LPDDR3. Elpida announced just at the end of the year that it has started shipping samples of 4Gbit SDRAMs with both interface types based … Continue reading →

Posted in LPDDR, LPDDR2, LPDDR3, Wide I/O | Tagged , , , , | 2 Comments