Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
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Recent Posts
- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
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Category Archives: SDRAM
IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
IDT has announced a small but essential component for the development of advanced DDR4 DIMMs: the 4RCD0124 DDR4 register. A device of this type is required for building DDR4 DIMMs to provide registered buffering. In addition, the 4RCD0124 DDR4 register … Continue reading
How ya gonna’ control that DDR4 SDRAM next year? The 28nm answer.
Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, SDRAM
Tagged DDR3 SDRAM, DDR4 SDRAM, JEDEC, Micron, Micron Technology, Samsung, technology, TSMC
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What does Intel’s choice of GDDR5 graphics DRAM for main memory with its Manycore Xeon Phi coprocessor say about SoC design?
George Chrysos discussed the Intel MIC (Many Integrated Core) architecture of the Knights Bridge chip (officially called the Intel Xeon Phi coprocessor) at today’s Hot Chips 24 conference and disclosed that it uses GDDR5 graphics memory as the main memory … Continue reading
Friday Video: A personal invitation to Memcon from Sanjay Srivastava
Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading
Test your system design for DDR4 JEDEC compliance with this $4500 ‘Scope add-on
Agilent has just announced a compliance test application for DDR4 SDRAM system designs. The $4500 Agilent N6462A DDR4 test application accelerates bring-up and debugging of DDR4 SDRAM-based systems by automating a bevy of physical-layer I/O testing with the company’s 9000 … Continue reading
Posted in DDR, DDR4, DRAM, SDRAM
Tagged Agilent, Agilent Technologies, DDR4 SDRAM, JEDEC, Memcon, Oscilloscope
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Save the date: JEDEC DDR4 Workshop, Santa Clara, CA. October 30-31
JEDEC is sponsoring a 2-day DDR4 workshop that should interest anyone planning on using DDR4 SDRAM in next-generation designs. Day 1: DDR4 vs DDR3: Comparison Matrix Why migrate to DDR4 Power-on, initialization, and training Read/Write and refresh operation review Day … Continue reading
How many DRAMs does it take to populate a supercomputer? 746,496 plus a lot of hot water for cooling
Jim Handy, The Memory Guy, posted a short blog about the 3-petaFLOP (peak) SuperMUC supercomputer at the Leibniz Supercomputing Centre on the outskirts of Munich, Germany. (The “MUC” in SuperMUC is the 3-letter code for the Munich airport. Now that’s … Continue reading
Micron announces volume production of PCM/DRAM multichip packaged memory
Totally not expecting this. Today Micron announced high-volume availability of a multichip, packaged memory device that incorporates a 1Gbit PCM (Phase-Change Memory) and a 512Mbit LPDDR2 SDRAM. The PCM die is built with 45nm process technology. The multichip-packaged memory is … Continue reading
Samsung’s 20nm-class DDR3 SDRAM runs on 1.35V, saves 2/3 of the power used by 50nm-class, 1.5V SDRAM
Not all DDR3 SDRAM is created equal. That’s the message Samsung is spreading lately by talking about its 20nm-class DDR3 SDRAM. The company is using 1.5V, 50nm-class DDR3 SDRAM as a benchmark and says that a server loaded with 96Mbytes … Continue reading
Want a quick and dirty overview of the new JEDEC LPDDR3 spec? EETimes serves it up
Kristin Lewotsky has just published an LPDDR3 SDRAM interview with Huong Vuong, Chairman of the JEDEC JC-42.6 Subcommittee for Low Power Memories. Here are the salient points from the interview, in my opinion: The purpose of LPDDR3 is to increase … Continue reading
Semiconductor memory plays a large role in smartphone design says Matti Floman of Nokia
“There’s no real difference between PCs and mobile phones today,” said Matti Floman from Nokia who gave the first keynote speech at last week’s JEDEC Mobile Forum. There is no difference in the types of applications run; there’s no difference … Continue reading
Micron samples DDR4 module at 2400Mtransfers/sec. Production pegged in 2013
Micron has begun sampling a DDR4 SDRAM module, which the company has said will lead the way to DDR4 availability in production equipment starting in 2013. The memory chips on the Micron DDR4 module are 30nm, 4Gbit, x8 parts operating … Continue reading
Posted in DDR4, DRAM, JEDEC, SDRAM
Tagged DDR4 SDRAM, JEDEC, Micron, Micron Technology, Nanya, SDRAM, SO-DIMM
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Simple three-bar graph explains all the engineering economics of 3D memory you need to know
The January IEEE Spectrum contained an article titled “3-D Chips Grow Up.” The article reproduced a simple Samsung bar graph about the very real advantages of 3D memory interconnect. That graph tells you all you need to know about why … Continue reading
Multicore, the Memory Wall, and Numerical Compression—FREE Webcast now available
Last month I posted a review of Al Wegener’s terrific IEEE Computer Society presentation at Cadence titled “Multicore, the Memory Wall, and Numerical Compression.” (See “Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? … Continue reading
Posted in DRAM, SDRAM, SRAM
Tagged IEEE Computer Society, memory, Multi-core processor, Samplify Systems, Wegener
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Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products… we need low-cost 3D IC assembly”
Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including … Continue reading
Posted in 3D, DRAM, SDRAM, Wide I/O
Tagged Computer History Museum, GSM, Holy Grail, JEDEC, Qualcomm
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DDR4 DIMM and SO-DIMM interposer modules work with Agilent logic analyzers
FuturePlus Systems has announced a pair of DDR4 SDRAM interposer modules compatible with Agilent logic analyzers to aid in hardware debugging of DDR4-based memory systems. The FS2501 interposer module works with DDR4 DIMMs at transfer rates to 2133Mtransfer/sec and the … Continue reading
Posted in DDR4, SDRAM
Tagged Agilent, Agilent Technologies, DDR4 SDRAM, DIMM, Logic analyzer, SO-DIMM
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A possible roadmap for Wide I/O that leads to 2Tbps of SDRAM memory bandwidth—per device
Cadence Product Marketing Director Marc Greenberg—one of the speakers at last week’s EDPS conference held in Monterey, California—spoke about why the Wide I/O SDRAM is probably the “killer app” that unleashes 3D IC assembly into the mainstream. Richard Goering has … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, SDRAM, Wide I/O
Tagged DDR SDRAM, Double data rate, JEDEC, Memory bandwidth, Wide I/O
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ISQED: Who and what will win the Universal Memory Derby?
Professor Cristophe Muller of Aix-Marseille University gave an excellent overview of non-volatile semiconductor memory as the third ISQED keynote this week. It’s a very good overview of today’s landscape and well worth discussing in a wider forum like this blog. … Continue reading
Where does LPDDR3 SDRAM fit in the low-power memory universe? How about Wide I/O SDRAM?
Marc Greenberg, Director of Product Marketing in the Cadence SoC Realization Design IP Group, just sent me some slides in connection with the recent introduction of the Cadence design and verification IP portfolio for LPDDR3 low-power SDRAM. I’ve already written … Continue reading
Upgrading your mobile or low-power SoC to LPDDR3? Got the right IP? You’ll need it to get maximum performance at minimum power
LPDDR3 is JEDEC’s next click on the low-power LPDDR SDRAM standard for mobile, portable, and other low-power devices. According to the JEDEC Web site, the LPDDR3 standard is still in development but the technical specs of the early devices announced … Continue reading
Want to avoid losing more than half of your SDRAM’s bandwidth? The right SDRAM controller configuration can help prevent the loss. Just ask Vivante.
Graphics processors (GPUs) suck bits out of SDRAMs the way vampires do what comes naturally to them in the immensely popular Twilight book series by Stephenie Meyer. In other words, GPUs need all the memory bandwidth they can get and … Continue reading
Agilent: Memory technology has hit a wall due to physics limitations and that has implications for your designs
Last week, Agilent ran a seminar in Milpitas, California. The first of three subseminars was about memory technology with an excellent overview of the state of memory technology today. It was presented by Gordon Getty, an Agilent Application Engineer based … Continue reading
Get the specifics of designing DDR3 SDRAM into a pcb with timing closure and good signal integrity
Next week at CDNLive!, EMA Design Automation will give a presentation on designing DDR3 SDRAM into a pcb with attention given to the signal integrity issues and timing closure. This session is one of seven pcb-specific sessions at CDNLive! on … Continue reading
More DDR4, DDR3, and 3D IC technical details from ISSCC, courtesy of memory analyst and expert Jim Handy
Semiconductor memory analyst and expert Jim Handy has just published an overview of some memory papers given at last week’s ISSCC. Handy’s article on the ElectroIQ web site supplements some of the previous Denali Memory Report blog entries published earlier … Continue reading
SanDisk’s founder and retired CEO Eli Harari says that the future of SSDs, computer memory, and everything else belongs to memristors at 11nm
The SSD Review reports that SanDisk’s founder and retired CEO Eli Harari delivered some explosive predictions at last week’s ISSCC in San Francisco. In sharp contrast to the recent and highly publicized paper predicting the slowdown of SSD speed and reliability … Continue reading
Operational DDR4 SDRAM prototypes appear at ISSCC
As reported this week by several Web sites including Techeye.net, Samsung and Hynix both demonstrated working prototypes of DDR4 SDRAM at the ISSCC conference in San Francisco this week. The Samsung and Hynix DDR4 memories were manufactured in 30nm and … Continue reading
Posted in DDR4, SDRAM
Tagged DDR4, Elpida, Elpida Memory, Hynix, International Solid-State Circuits Conference, ISSCC, Micron Technology, Samsung, SDRAM, Server memory
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Is Wide I/O SDRAM a disruptive technology? Signs say yes according to new EETimes article
A new article about Wide I/O and 3D IC assembly published in EETimes brings some additional technical information to light. The article was written by Marc Greenberg and Samta Bansal, both from Cadence, and it contains both a review of … Continue reading
Is Wide I/O SDRAM free for the end user? (Republished from EDA360 Insider)
Note: I just published this blog entry on my EDA360 Insider blog for 3D Thursday but the topic is so relevant to the conversation in the Denali Memory Report that I am republishing it here as well. A recent email … Continue reading
LeCroy introduces DDR4 Bus and Timing Analyzer at DesignCon 2012
LeCroy’s Kibra 480 DDR bus and timing analyzer now lets you analyze bust traffic on DDR4 interfaces at the board and connector level. It is an evolution from the company’s earlier Kibra 380 DDR3 bus and timing analyzer. (See “How … Continue reading
JEDEC to hold free server memory forum in Shenzen, March 1
Anyone involved in the development and use of server memory will want to consider the free server memory forum that JEDEC will be holding in Shenzen, China on March 1. Current agenda: Server memory roadmaps and trends DDR4 as enterprise … Continue reading
Big week for Wide I/O: JEDEC publishes spec while Elpida ships sample 4Gbit parts
Wide I/O jumped closer to being a reality this week with two major announcements. On December 28th, Elpida announced that they were making sample shipments of 4Gbit Wide-IO. (See “Let’s start the new year with a bang! Elpida ships 4Gbit … Continue reading
Posted in JEDEC, LPDDR2, SDRAM, Wide I/O
Tagged Elpida, Elpida Memory, JEDEC, LPDDR2, SDRAM, ST-Ericsson, Wide I/O
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