Category Archives: SDRAM

IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks

IDT has announced a small but essential component for the development of advanced DDR4 DIMMs: the 4RCD0124 DDR4 register. A device of this type is required for building DDR4 DIMMs to provide registered buffering. In addition, the 4RCD0124 DDR4 register … Continue reading

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How ya gonna’ control that DDR4 SDRAM next year? The 28nm answer.

Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with … Continue reading

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What does Intel’s choice of GDDR5 graphics DRAM for main memory with its Manycore Xeon Phi coprocessor say about SoC design?

George Chrysos discussed the Intel MIC (Many Integrated Core) architecture of the Knights Bridge chip (officially called the Intel Xeon Phi coprocessor) at today’s Hot Chips 24 conference and disclosed that it uses GDDR5 graphics memory as the main memory … Continue reading

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Friday Video: A personal invitation to Memcon from Sanjay Srivastava

Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading

Posted in DDR3, DDR4, DRAM, Flash, HMC, Hybrid Memory Cube, JEDEC, LPDDR2, LPDDR3, LPDDR4, Memcon, MRAM, mSATA, NAND, NOR, NVM Express, NVMe, ONFI, PCIe, Samsung, SAS, SATA, SD, SDRAM | Tagged , , , | Leave a comment

Test your system design for DDR4 JEDEC compliance with this $4500 ‘Scope add-on

Agilent has just announced a compliance test application for DDR4 SDRAM system designs. The $4500 Agilent N6462A DDR4 test application accelerates bring-up and debugging of DDR4 SDRAM-based systems by automating a bevy of physical-layer I/O testing with the company’s 9000 … Continue reading

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Save the date: JEDEC DDR4 Workshop, Santa Clara, CA. October 30-31

JEDEC is sponsoring a 2-day DDR4 workshop that should interest anyone planning on using DDR4 SDRAM in next-generation designs. Day 1: DDR4 vs DDR3: Comparison Matrix Why migrate to DDR4 Power-on, initialization, and training Read/Write and refresh operation review Day … Continue reading

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How many DRAMs does it take to populate a supercomputer? 746,496 plus a lot of hot water for cooling

Jim Handy, The Memory Guy, posted a short blog about the 3-petaFLOP (peak) SuperMUC supercomputer at the Leibniz Supercomputing Centre on the outskirts of Munich, Germany. (The “MUC” in SuperMUC is the 3-letter code for the Munich airport. Now that’s … Continue reading

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