Category Archives: DDR

How ya gonna’ control that DDR4 SDRAM next year? The 28nm answer.

Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with … Continue reading

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What does Intel’s choice of GDDR5 graphics DRAM for main memory with its Manycore Xeon Phi coprocessor say about SoC design?

George Chrysos discussed the Intel MIC (Many Integrated Core) architecture of the Knights Bridge chip (officially called the Intel Xeon Phi coprocessor) at today’s Hot Chips 24 conference and disclosed that it uses GDDR5 graphics memory as the main memory … Continue reading

Posted in DDR, HMC, Hybrid Memory Cube, SDRAM | Tagged , , , , , | 1 Comment

Test your system design for DDR4 JEDEC compliance with this $4500 ‘Scope add-on

Agilent has just announced a compliance test application for DDR4 SDRAM system designs. The $4500 Agilent N6462A DDR4 test application accelerates bring-up and debugging of DDR4 SDRAM-based systems by automating a bevy of physical-layer I/O testing with the company’s 9000 … Continue reading

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See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video

This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading

Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, LPDDR3, Wide I/O | Tagged , , , | Leave a comment

Who do you want to see at Memcon?

As the emcee for the Memcon event on September 18, I’ve been given the opportunity to personally invite a few, select exhibitors to the show and to cut them a very sweet deal. To do that, I’d like to know … Continue reading

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Want more details about the new Micron 1Gbit Phase-Change Memory / 512Mbit SDRAM device? Here are several

Yesterday, Micron announced volume production of a new memory device containing one 1Gbit PCM (phase-change memory) die and one 512Mbit LPDDR2 SDRAM die. This morning, I had a conversation about this new device with Philippe Berge—Senior Director of the NOR, … Continue reading

Posted in DDR, Flash, LPDDR2, Micron, NOR, PCM, Storage | Tagged , , , , , , , | Leave a comment

Want another opinion about the Hybrid Memory Cube? Michael Feldman of HPCwire.com weighs in

Michael Feldman over at HPCwire.com has just published his own analysis of the Hybrid Memory Cube (HMC), which I’ve covered extensively in the EDA360 Insider and the Denali Memory Report (see below). Feldman reiterates many of the same points I’ve … Continue reading

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