Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
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- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
What's hot on the Denali Memory Report?
- Compact Flash
- Hybrid Memory Cube
- NVM Express
- Wide I/O
Category Archives: Hybrid Memory Cube
What does Intel’s choice of GDDR5 graphics DRAM for main memory with its Manycore Xeon Phi coprocessor say about SoC design?
George Chrysos discussed the Intel MIC (Many Integrated Core) architecture of the Knights Bridge chip (officially called the Intel Xeon Phi coprocessor) at today’s Hot Chips 24 conference and disclosed that it uses GDDR5 graphics memory as the main memory … Continue reading
Memcon is filling up. Register now to be sure you get a ticket. It’s free. September 18. Silicon Valley
The Flash Memory Summit took place this week and registration for next month’s Memcon in Silicon Valley suddenly took a big uptick. I’d like to suggest that if you want to be certain to attend Memcon next month, you might … Continue reading
Posted in DRAM, Flash, HMC, Hybrid Memory Cube Tagged DRAM, Flash, Memcon Leave a comment
Friday Video: A personal invitation to Memcon from Sanjay Srivastava
Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading
Initial Hybrid Memory Cube short-reach interconnect specification issued to Consortium adopters
The Hybrid Memory Cube Consortium (HMCC), now supported by the three top DRAM vendors (Samsung, SK hynix, and Micron), has just issued an initial draft specification for the Hybrid Memory Cube’s “short-reach interconnection across physical layers”—in other words, the short-reach … Continue reading
Posted in 3D, DRAM, HMC, Hybrid Memory Cube, Hynix, Micron, Samsung Tagged Hybrid Memory Cube, IBM, Micron, MicronTechnology, PHY, Samsung, SerDes Leave a comment
Want another opinion about the Hybrid Memory Cube? Michael Feldman of HPCwire.com weighs in
Michael Feldman over at HPCwire.com has just published his own analysis of the Hybrid Memory Cube (HMC), which I’ve covered extensively in the EDA360 Insider and the Denali Memory Report (see below). Feldman reiterates many of the same points I’ve … Continue reading
Posted in DDR, DRAM, HMC, Hybrid Memory Cube, Micron Tagged DRAM, Dynamic random-access memory, Flash memory, HMC, Michael Feldman, Micron Leave a comment
MOSAID and NOVACHIPS announce plans for an HLNAND-based SSD controller chip. Release set for 2013.
A couple of weeks ago, MOSAID and NOVACHIPS announced plans to jointly develop an SSD controller based on the MOSAID high-speed HLNAND interface specification. If you’re not familiar with the MOSAID HLNAND high-speed serial interface, join the club. Most NAND … Continue reading
Posted in 3D, Flash, Hybrid Memory Cube, NAND Tagged Flash memory, Flash memory controller, HyperLink, MOSAID, NAND Flash, NOVACHIPS, PCI Express, Solid-state drive, SSD 1 Comment
ARM, HP, and SK hynix join Hybrid Memory Cube Consortium (HMCC). First spec due by end of year
Add ARM, HP, and SK hynix to the growing list of companies in the Hybrid Memory Cube Consortium (HMCC). The three new members join the original founding companies, Micron and Samsung, along with Altera, IBM, Microsoft, Open-Silicon, and Xilinx plus … Continue reading
It’s Official: Microsoft joins 3D Hybrid Memory Cube Consortium with Micron, Samsung, Altera, IBM, Open-Silicon, and Xilinx
Last week, the Hybrid Memory Cube Consortium announced that Microsoft had joined Micron, Samsung, Altera, IBM, Open-Silicon, and Xilinx in the development of high-performance 3D SDRAM subsystems based on the Hybrid Memory Cube. For more information on the Hybrid Memory … Continue reading
Posted in 3D, DRAM, HMC, Hybrid Memory Cube Tagged Altera, Hybrid Memory Cube, IBM, Micron, Microsoft, Open-Silicon, Samsung, Xilinx Leave a comment
Want some additional details about the Micron Hybrid Memory Cube?
This week at Design West (the conference previously known as the Embedded Systems Conference), I had a chance to speak with Mike Black from Micron about the Hybrid Memory Cube (HMC), a 3D DRAM assembly aimed at high-performance computing. The … Continue reading
Posted in 3D, DRAM, HMC, Hybrid Memory Cube Tagged Altera, FPGA, HMC, Hybrid Memory Cube, IBM Leave a comment
Microprocessor Report names Micron Hybrid Memory Cube as “Best Microprocessor Technology” of the year
This week, Microprocessor Report selected the Micron Hybrid Memory Cube (HMC) as the “Best Microprocessor Technology” of 2011. Why? As Tom Halfhill writes: “Memory cubes promise greater density, lower latency, higher bandwidth, and better power efficiency per bit compared with … Continue reading
Posted in 3D, DRAM, Hybrid Memory Cube Tagged HMC, Hybrid Memory Cube, Micron Leave a comment