Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
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- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
What's hot on the Denali Memory Report?
- Compact Flash
- Hybrid Memory Cube
- NVM Express
- Wide I/O
Tag Archives: DDR3 SDRAM
How ya gonna’ control that DDR4 SDRAM next year? The 28nm answer.
Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, SDRAM Tagged DDR3 SDRAM, DDR4 SDRAM, JEDEC, Micron, Micron Technology, Samsung, technology, TSMC Leave a comment
See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video
This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, LPDDR3, Wide I/O Tagged DDR3 SDRAM, DDR4 SDRAM, DRAM, SDRAM Leave a comment
Samsung’s 20nm-class DDR3 SDRAM runs on 1.35V, saves 2/3 of the power used by 50nm-class, 1.5V SDRAM
Not all DDR3 SDRAM is created equal. That’s the message Samsung is spreading lately by talking about its 20nm-class DDR3 SDRAM. The company is using 1.5V, 50nm-class DDR3 SDRAM as a benchmark and says that a server loaded with 96Mbytes … Continue reading
Designing circuit boards with DDR3? Full-day, hands-on tutorial in Europe shows you how. Munich, May 14
System designs employing DDR3 SDRAMs present many new pcb design challenges compared to DDR2. DDR3 clock, address, and control lines employ a new fly-by topology; setup and hold times need to be just right because there are reduced timing margins … Continue reading
Posted in DDR3 Tagged DDR3 SDRAM, Design, Munich, PCB Design, Printed circuit board Leave a comment
DRAMeXchange opines on six major DRAM and NAND Flash trends for 2012-2015. What do you think?
The DRAMeXchange http://www.dramexchange.com/ keeps a very close watch on the spot and contract prices for all forms of semiconductor memory including DRAM and NAND Flash devices. The group also keeps an eye on trends that may affect pricing. A couple … Continue reading
Posted in 3D, DDR3, DDR4, DRAM, Flash, HDD, LPDDR2, LPDDR3, Memcon, ONFI, Toggle Tagged DDR3 SDRAM, Flash, Flash memory, NAND Flash, PCI Express, Ultrabook Leave a comment
More DDR4, DDR3, and 3D IC technical details from ISSCC, courtesy of memory analyst and expert Jim Handy
Semiconductor memory analyst and expert Jim Handy has just published an overview of some memory papers given at last week’s ISSCC. Handy’s article on the ElectroIQ web site supplements some of the previous Denali Memory Report blog entries published earlier … Continue reading
LeCroy introduces DDR4 Bus and Timing Analyzer at DesignCon 2012
LeCroy’s Kibra 480 DDR bus and timing analyzer now lets you analyze bust traffic on DDR4 interfaces at the board and connector level. It is an evolution from the company’s earlier Kibra 380 DDR3 bus and timing analyzer. (See “How … Continue reading
Posted in DDR3, DDR4, DRAM, SDRAM Tagged DDR3 SDRAM, DDR4 SDRAM, LeCroy Corporation Leave a comment