Monthly Archives: May 2012

MRAM spotted in Buffalo Memory SSD—for cache

Several sources including TomsHardware.com have reported the appearance at the 15th Embedded Systems Expo in Japan of an SSD built by Buffalo Memory Company with MRAM for cache memory. The drive uses 8Mbytes of MRAM (magnetic RAM) as a cache … Continue reading

Posted in Flash, MRAM, SSD | Tagged , , , | 1 Comment

This SSD will self destruct…immediately. On Command (See the video)

In case you need an SSD that can be wiped quickly, RunCore has introduced the InVincible SSD with two modes of erasure: non-destructive and destructive. Two buttons—one red, one green—activate the erasure. The two buttons apparently connect to the SSD’s … Continue reading

Posted in SSD | Tagged , , , , | 2 Comments

DFI 3.1 spec adds DDR4 and LPDDR3 coverage for speed and low-power benefits

Earlier this month, JEDEC published the LPDDR3 specification for the next generation of low-power SDRAM that will be used in mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks. The LPDDR3 … Continue reading

Posted in DDR, DDR4, DFI, JEDEC, LPDDR3 | Tagged , , , , | Leave a comment

Invensas to detail POP interconnect to rival Wide I/O with as many as 1200 interconnections between IC packages

Later this week, Invensas will detail its new BVA (bond via array) package-on-package (POP) interconnect that can achieve 1200 electrical connections between chip packages without the use of 3D die assembly. Information on the technology will be contained in a … Continue reading

Posted in 3D, Wide I/O | Tagged , , , | Leave a comment

The Denali Memory Report is on vacation and will return on May 26, 2012

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Semiconductor memory plays a large role in smartphone design says Matti Floman of Nokia

“There’s no real difference between PCs and mobile phones today,” said Matti Floman from Nokia who gave the first keynote speech at last week’s JEDEC Mobile Forum. There is no difference in the types of applications run; there’s no difference … Continue reading

Posted in 3D, DDR, LPDDR2, Memristor, MRAM, SDRAM, Storage, UFS | Tagged , , , , , | Leave a comment

NVM Express (NVMe) controller subsystem points the way to an SSD future

Cadence introduced an NVM Express (NVMe) controller subsystem this week. The Denali Memory Report and the EDA360 Insider have covered NVMe developments several times already (see below for the links) and it’s clear that one way to maximize SSD performance … Continue reading

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