Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
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Recent Posts
- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
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Tag Archives: SDRAM
See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video
This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading
Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, LPDDR3, Wide I/O
Tagged DDR3 SDRAM, DDR4 SDRAM, DRAM, SDRAM
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Who do you want to see at Memcon?
As the emcee for the Memcon event on September 18, I’ve been given the opportunity to personally invite a few, select exhibitors to the show and to cut them a very sweet deal. To do that, I’d like to know … Continue reading
Micron announces volume production of PCM/DRAM multichip packaged memory
Totally not expecting this. Today Micron announced high-volume availability of a multichip, packaged memory device that incorporates a 1Gbit PCM (Phase-Change Memory) and a 512Mbit LPDDR2 SDRAM. The PCM die is built with 45nm process technology. The multichip-packaged memory is … Continue reading
Second Samsung memory video just as amusing as the first
Yesterday, I posted a blog entry about an amusing Samsung memory video aimed at memory consumers with a fanciful supervillian named Fiona Freeze who was responsible for causing device freezups. Today, I present the Samsung Memory Battery Brutus video. Battery … Continue reading
Samsung’s 20nm-class DDR3 SDRAM runs on 1.35V, saves 2/3 of the power used by 50nm-class, 1.5V SDRAM
Not all DDR3 SDRAM is created equal. That’s the message Samsung is spreading lately by talking about its 20nm-class DDR3 SDRAM. The company is using 1.5V, 50nm-class DDR3 SDRAM as a benchmark and says that a server loaded with 96Mbytes … Continue reading
Want a quick and dirty overview of the new JEDEC LPDDR3 spec? EETimes serves it up
Kristin Lewotsky has just published an LPDDR3 SDRAM interview with Huong Vuong, Chairman of the JEDEC JC-42.6 Subcommittee for Low Power Memories. Here are the salient points from the interview, in my opinion: The purpose of LPDDR3 is to increase … Continue reading
Semiconductor memory plays a large role in smartphone design says Matti Floman of Nokia
“There’s no real difference between PCs and mobile phones today,” said Matti Floman from Nokia who gave the first keynote speech at last week’s JEDEC Mobile Forum. There is no difference in the types of applications run; there’s no difference … Continue reading
Micron samples DDR4 module at 2400Mtransfers/sec. Production pegged in 2013
Micron has begun sampling a DDR4 SDRAM module, which the company has said will lead the way to DDR4 availability in production equipment starting in 2013. The memory chips on the Micron DDR4 module are 30nm, 4Gbit, x8 parts operating … Continue reading
Posted in DDR4, DRAM, JEDEC, SDRAM
Tagged DDR4 SDRAM, JEDEC, Micron, Micron Technology, Nanya, SDRAM, SO-DIMM
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Memcon 2012 call for presentation submissions
Memcon 2012 will take place at the Santa Clara Convention Center in the heart of Silicon Valley on Tuesday, September 2012. This is the biggest conference in the world devoted to the use and manufacture of semiconductor memory (RAM, NAND … Continue reading
Want to avoid losing more than half of your SDRAM’s bandwidth? The right SDRAM controller configuration can help prevent the loss. Just ask Vivante.
Graphics processors (GPUs) suck bits out of SDRAMs the way vampires do what comes naturally to them in the immensely popular Twilight book series by Stephenie Meyer. In other words, GPUs need all the memory bandwidth they can get and … Continue reading
Get the specifics of designing DDR3 SDRAM into a pcb with timing closure and good signal integrity
Next week at CDNLive!, EMA Design Automation will give a presentation on designing DDR3 SDRAM into a pcb with attention given to the signal integrity issues and timing closure. This session is one of seven pcb-specific sessions at CDNLive! on … Continue reading
Operational DDR4 SDRAM prototypes appear at ISSCC
As reported this week by several Web sites including Techeye.net, Samsung and Hynix both demonstrated working prototypes of DDR4 SDRAM at the ISSCC conference in San Francisco this week. The Samsung and Hynix DDR4 memories were manufactured in 30nm and … Continue reading
Posted in DDR4, SDRAM
Tagged DDR4, Elpida, Elpida Memory, Hynix, International Solid-State Circuits Conference, ISSCC, Micron Technology, Samsung, SDRAM, Server memory
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Is Wide I/O SDRAM a disruptive technology? Signs say yes according to new EETimes article
A new article about Wide I/O and 3D IC assembly published in EETimes brings some additional technical information to light. The article was written by Marc Greenberg and Samta Bansal, both from Cadence, and it contains both a review of … Continue reading
STT MRAM startup Spin Transfer Technologies secures $36M in Series A funding
Last week, STT MRAM startup Spin Transfer Technologies announced that it had secured $36M in Series A financing from Allied Minds and Invesco Asset Management. Spin Transfer Technologies is developing an “orthogonal” version of STT (spin transfer technology—the technology, not … Continue reading
Posted in Flash, MRAM, NAND
Tagged Flash, Flash memory, Magnetoresistive random access memory, MRAM, NAND, SDRAM, Spin torque transfer
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Is Wide I/O SDRAM free for the end user? (Republished from EDA360 Insider)
Note: I just published this blog entry on my EDA360 Insider blog for 3D Thursday but the topic is so relevant to the conversation in the Denali Memory Report that I am republishing it here as well. A recent email … Continue reading
Memcon 2012: Save the date—September 18, 2012 in Santa Clara CA
The date’s official! The 2012 edition of Memcon—the conference devoted to all aspects of semiconductor memory design, manufacture, and use—will take place at the Santa Clara Convention Center on September 18, 2012. So put that date on your calendar now, … Continue reading
The return of Memcon in 2012
Under the leadership of Denali Software, Memcon became the single most important event for the semiconductor memory and storage industries. Now Cadence is taking that legacy into the future. Yes, that’s right, Memcon is back for 2012 as a standalone … Continue reading
Big week for Wide I/O: JEDEC publishes spec while Elpida ships sample 4Gbit parts
Wide I/O jumped closer to being a reality this week with two major announcements. On December 28th, Elpida announced that they were making sample shipments of 4Gbit Wide-IO. (See “Let’s start the new year with a bang! Elpida ships 4Gbit … Continue reading
Posted in JEDEC, LPDDR2, SDRAM, Wide I/O
Tagged Elpida, Elpida Memory, JEDEC, LPDDR2, SDRAM, ST-Ericsson, Wide I/O
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