Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
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Recent Posts
- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
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Tag Archives: PHY
Initial Hybrid Memory Cube short-reach interconnect specification issued to Consortium adopters
The Hybrid Memory Cube Consortium (HMCC), now supported by the three top DRAM vendors (Samsung, SK hynix, and Micron), has just issued an initial draft specification for the Hybrid Memory Cube’s “short-reach interconnection across physical layers”—in other words, the short-reach … Continue reading
Posted in 3D, DRAM, HMC, Hybrid Memory Cube, Hynix, Micron, Samsung
Tagged Hybrid Memory Cube, IBM, Micron, MicronTechnology, PHY, Samsung, SerDes
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DFI 3.1 spec adds DDR4 and LPDDR3 coverage for speed and low-power benefits
Earlier this month, JEDEC published the LPDDR3 specification for the next generation of low-power SDRAM that will be used in mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks. The LPDDR3 … Continue reading
NVM Express (NVMe) controller subsystem points the way to an SSD future
Cadence introduced an NVM Express (NVMe) controller subsystem this week. The Denali Memory Report and the EDA360 Insider have covered NVMe developments several times already (see below for the links) and it’s clear that one way to maximize SSD performance … Continue reading
A detailed look at the IP components of an SSD controller chip by Dr. Eric Esteve
IPNEST blogger and analyst Dr. Eric Esteve has just published a detailed look at many of the IP components needed to design a high-performance SSD controller chip including a NAND Flash controller and high-speed PHY interface for NAND Flash devices. … Continue reading
Posted in Flash, NAND, NVMe, ONFI
Tagged Eric Esteve, Flash memory, Flash memory controller, NAND Flash, ONFI, PHY, Solid-state drive, SSD
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