Tag Archives: PHY

Initial Hybrid Memory Cube short-reach interconnect specification issued to Consortium adopters

The Hybrid Memory Cube Consortium (HMCC), now supported by the three top DRAM vendors (Samsung, SK hynix, and Micron), has just issued an initial draft specification for the Hybrid Memory Cube’s “short-reach interconnection across physical layers”—in other words, the short-reach … Continue reading

Posted in 3D, DRAM, HMC, Hybrid Memory Cube, Hynix, Micron, Samsung | Tagged , , , , , , | Leave a comment

DFI 3.1 spec adds DDR4 and LPDDR3 coverage for speed and low-power benefits

Earlier this month, JEDEC published the LPDDR3 specification for the next generation of low-power SDRAM that will be used in mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks. The LPDDR3 … Continue reading

Posted in DDR, DDR4, DFI, JEDEC, LPDDR3 | Tagged , , , , | Leave a comment

NVM Express (NVMe) controller subsystem points the way to an SSD future

Cadence introduced an NVM Express (NVMe) controller subsystem this week. The Denali Memory Report and the EDA360 Insider have covered NVMe developments several times already (see below for the links) and it’s clear that one way to maximize SSD performance … Continue reading

Posted in NVM Express, SSD | Tagged , , , , | Leave a comment

A detailed look at the IP components of an SSD controller chip by Dr. Eric Esteve

IPNEST blogger and analyst Dr. Eric Esteve has just published a detailed look at many of the IP components needed to design a high-performance SSD controller chip including a NAND Flash controller and high-speed PHY interface for NAND Flash devices. … Continue reading

Posted in Flash, NAND, NVMe, ONFI | Tagged , , , , , , , | Leave a comment