Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
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Recent Posts
- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
Archives
What's hot on the Denali Memory Report?
Categories
- 3D
- ARM
- Compact Flash
- Cortex-A15
- DDR
- DDR3
- DDR4
- DFI
- DRAM
- eMMC
- Ethernet
- Exynos
- Flash
- HDD
- HMC
- Hybrid Memory Cube
- Hynix
- JEDEC
- LeCroy
- LPDDR
- LPDDR2
- LPDDR3
- LPDDR3E
- LPDDR4
- LRDIMM
- Marvell
- MCP
- Memcon
- Memristor
- Micron
- MLC
- MRAM
- mSATA
- NAND
- NOR
- NVM Express
- NVMe
- ONFI
- PCIe
- PCM
- QDR
- ReRAM
- Samsung
- SAS
- SATA
- SD
- SDRAM
- SLC
- SRAM
- SSD
- Storage
- Toggle
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- Uncategorized
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- Wide I/O
- XQD
Meta
Tag Archives: PCB Design
Designing circuit boards with DDR3? Full-day, hands-on tutorial in Europe shows you how. Munich, May 14
System designs employing DDR3 SDRAMs present many new pcb design challenges compared to DDR2. DDR3 clock, address, and control lines employ a new fly-by topology; setup and hold times need to be just right because there are reduced timing margins … Continue reading
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