Tag Archives: LPDDR

Want a quick and dirty overview of the new JEDEC LPDDR3 spec? EETimes serves it up

Posted on June 13, 2012 by sleibson2

Kristin Lewotsky has just published an LPDDR3 SDRAM interview with Huong Vuong, Chairman of the JEDEC JC-42.6 Subcommittee for Low Power Memories. Here are the salient points from the interview, in my opinion: The purpose of LPDDR3 is to increase … Continue reading →

Posted in LPDDR2, LPDDR3, LPDDR3E, LPDDR4, SDRAM | Tagged , , , , , , | Leave a comment

Agilent: Memory technology has hit a wall due to physics limitations and that has implications for your designs

Posted on March 12, 2012 by sleibson2

Last week, Agilent ran a seminar in Milpitas, California. The first of three subseminars was about memory technology with an excellent overview of the state of memory technology today. It was presented by Gordon Getty, an Agilent Application Engineer based … Continue reading →

Posted in 3D, DDR3, DDR4, DRAM, eMMC, Flash, LPDDR2, LPDDR3, NAND, NOR, QDR, SD, SDRAM, Storage | Tagged , , , , , , , , , , , , | 1 Comment

Let’s start the new year with a bang! Elpida ships 4Gbit Wide I/O and LPDDR3 SDRAM samples

Posted on January 5, 2012 by sleibson2

Two DRAM categories that will shake up mobile product design this year are Wide I/O and LPDDR3. Elpida announced just at the end of the year that it has started shipping samples of 4Gbit SDRAMs with both interface types based … Continue reading →

Posted in LPDDR, LPDDR2, LPDDR3, Wide I/O | Tagged , , , , | 2 Comments