Tag Archives: DDR SDRAM

DFI 3.1 spec adds DDR4 and LPDDR3 coverage for speed and low-power benefits

Posted on May 30, 2012 by sleibson2

Earlier this month, JEDEC published the LPDDR3 specification for the next generation of low-power SDRAM that will be used in mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks. The LPDDR3 … Continue reading →

Posted in DDR, DDR4, DFI, JEDEC, LPDDR3 | Tagged , , , , | Leave a comment

Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?

Posted on April 16, 2012 by sleibson2

Multicore SoC and processor designs were our solution to the death of Dennard Scaling when IC process geometries dropped below 90nm, when processor speeds hit 3GHz, and when processor power consumption went off the charts. Since 2004, we’ve transformed Moore’s … Continue reading →

Posted in 3D, DDR, DDR3, DDR4, DRAM, Flash, PCIe, Wide I/O | Tagged , , , | 9 Comments

A possible roadmap for Wide I/O that leads to 2Tbps of SDRAM memory bandwidth—per device

Posted on April 10, 2012 by sleibson2

Cadence Product Marketing Director Marc Greenberg—one of the speakers at last week’s EDPS conference held in Monterey, California—spoke about why the Wide I/O SDRAM is probably the “killer app” that unleashes 3D IC assembly into the mainstream. Richard Goering has … Continue reading →

Posted in DDR, DDR3, DDR4, DRAM, SDRAM, Wide I/O | Tagged , , , , | 2 Comments