Tag Archives: CDNLive!

Get the specifics of designing DDR3 SDRAM into a pcb with timing closure and good signal integrity

Next week at CDNLive!, EMA Design Automation will give a presentation on designing DDR3 SDRAM into a pcb with attention given to the signal integrity issues and timing closure. This session is one of seven pcb-specific sessions at CDNLive! on … Continue reading

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