Tag Archives: 3D

Applied Materials develops Centura Avatar etcher for enabling 3D NAND Flash manufacture

About a year ago, I wrote an EDA360 Insider blog entry about 3D NAND Flash semiconductor memory. (See “3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron”) In this post, I discussed a talk by Glen … Continue reading

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3D Thursday: Advantest 3D tester produces known good die and known good stacks

3D can’t move forward until the testability issues are solved. Hear that one? Well, Advantest has just advanced another click in that ratchet with this week’s introduction of a concept model test cell for TSV-based 2.5D and 3D products. It’s … Continue reading

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Invensas to detail POP interconnect to rival Wide I/O with as many as 1200 interconnections between IC packages

Later this week, Invensas will detail its new BVA (bond via array) package-on-package (POP) interconnect that can achieve 1200 electrical connections between chip packages without the use of 3D die assembly. Information on the technology will be contained in a … Continue reading

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Is Wide I/O SDRAM free for the end user? (Republished from EDA360 Insider)

Note: I just published this blog entry on my EDA360 Insider blog for 3D Thursday but the topic is so relevant to the conversation in the Denali Memory Report that I am republishing it here as well. A recent email … Continue reading

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Quickly Noted: EETimes on the challenges of testing semiconductor memory for mobile applications. Is testing really a 3D IC “stopper”?

Janine Love at EETimes interviewed Cecil Ho, President of CST (Simmtester.com)—a memory tester vendor, about issues surrounding the testing of semiconductor memory that’s optimized for and aimed at mobile applications. In these applications board real estate and physical volume are … Continue reading

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