25 Years of Removable Storage in One Photograph

Thomas Morffew published this amazing photo showing 25 years of removable storage artifacts. At the top are 5.25- and 3.5-inch floppy disks. Towards the bottom, in the center are some CDs and then comes the solid-state storage—memory sticks, SD cards, and Micro SD cards. The bottom-most Micro SD cards have so much storage capacity that they can each hold the contents of all of the other storage media in the picture. All spanning 25 years. What’s missing? 8-inch floppy disks, WORM (write-once, read mostly) optical media, and tape products.

Posted in Storage | Tagged , , , , , | 3 Comments

Multicore, the Memory Wall, and Numerical Compression—FREE Webcast now available

Last month I posted a review of Al Wegener’s terrific IEEE Computer Society presentation at Cadence titled “Multicore, the Memory Wall, and Numerical Compression.” (See “Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?”) Now, you can see the actual presentation as a recorded Webcast, for free. Wegener is the CTO, chairman, and founder of Samplify Systems and he has a firm grasp of the issues surrounding processor-memory and multicore-memory access. This information is an essential part of any sound processing architecture and now you can view it for free.

Click here.

Posted in DRAM, SDRAM, SRAM | Tagged , , , , | Leave a comment

Do you know the advantages and disadvantages of the six different use cases for SSDs?

Marc Staimer, founder and senior analyst at Dragon Slayer Consulting, has just published an excellent primer on locating SSD storage within a server and storage network. With the advent of PCIe-based SSD storage based on NAND Flash memory, the number of alternative uses for SSDs has grown and Staimer lists six such uses, plus the pros and cons for each use.

Here’s a brief summary of Staimler’s six use cases plus the advantages and disadvantages of each (see the full 2-part article for more in-depth information, registration needed):

1. PCIe SSD as server cache or storage


  • Low latency: no intervening adapters, transceivers, cables, switches, or controllers
  • Significantly improves transaction performance


  • Increases CPU utilization from 5% to 25%
  • Relatively low capacity caused by physical volume limitations
  • PCIe SSD cards in a server can’t be shared by multiple servers
  • Can’t be used by virtual servers

2. PCIe SSD as cache in a SAN or NAS storage system


  • Reduces latency from applications to shared storage
  • Can be shared by both physical and virtual servers
  • Works well with virtual servers


  • Cache size limited by the number of PCIe slots in the storage system
  • Caches cannot be shared across storage systems
  • May bottleneck the storage system’s CPU due to utilization load for the PCIe caches

3. SSDs with HDD form factor as NAS or as cache for a storage array


  • Reduces latency from applications to shared storage
  • Can be shared by both physical and virtual servers
  • Works well with virtual servers


  • Capacity limited by size of SSD
  • Performance limited by SSD controller
  • Cannot be shared across storage systems

4. SSDs with HDD form factor as Tier 0 storage in multi-tier NAS or storage array


  • Reduces latency from applications to shared storage
  • Requires no server resources
  • Can be shared by both physical and virtual servers
  • Works well with virtual servers
  • Can reduce the number of HDDs needed without compromising performance or capacity


  • Diminished ability to meet demand load as working sets grow
  • Only benefits the storage system in which it’s installed
  • Auto-tiering software increases load on the controller CPU with possible performance impact

5. SSDs with HDD form factor in an all-SSD NAS or storage array


  • Reduces latency from applications to shared storage
  • Only one storage tier—no complex tiering software to deal with
  • Works well with virtual servers
  • Consumes no server resources
  • Reduces power and cooling requirements for storage
  • Cost per IOPS conspicuously better


  • Limited scalability (currently 500Tbytes or less)
  • Storage controller is the bottleneck
  • Cost/capacity

6. SSDs with PCIe or HDD form factor as a cache appliance on the storage network


  • Reduces latency from applications to shared storage
  • Sharable among physical and virtual servers and multiple storage systems


  • Scalability may be limited to 10Tbytes or less
  • Extra subsystem (cache appliance) may complicate troubleshooting
Posted in Flash, HDD, SSD | Tagged , , , , , , , , , , | 1 Comment

Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products… we need low-cost 3D IC assembly”

Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including wafer fab process nodes, backend interconnect, and packaging technologies.

Qualcomm has been working on 3D IC technology development projects to help prepare the company for a 3D future. “3D DRAM stacking has started—it’s shipping in products because it has maintained the bit density/cost ratio,” said Yu. The next thing that will happen, he predicted, is memory stacked on logic. Yu then specifically mentioned Wide I/O and Wide I/O 2 SDRAM, which deliver more memory bandwidth at lower operating power than DDR memory. (See “3D Week: JEDEC Wide I/O Memory spec cleared for use” and “Where does LPDDR3 SDRAM fit in the low-power memory universe? How about Wide I/O SDRAM?”.)

The Holy Grail, said Yu, is full 3D IC assembly that fits RF, memory, power, logic, and sensor die into one package. “It will take a lot of hard work to make this happen,” he predicted. “The thermal envelope is perhaps the biggest limited factor, but power consumption is another major consideration,” Yu continued, “Batteries aren’t getting better. However, if we don’t make the cost structure right, it’s not going to happen for cellphones.”

“And cost drives everything,” he added, making that fact very clear with one slide. The slide showed two curves: GSM mobile handset unit cost over time and GSM mobile handset sales volume over time. “Once we dropped below $200,” said Yu, “worldwide sales really took off” referring to a sharp knee in the sales-volume curve that led to billion-unit annual sales. That’s why we need low-cost 3D IC assembly, continued Yu. “Cost opens the door to sales volume.”

Posted in 3D, DRAM, SDRAM, Wide I/O | Tagged , , , , | 1 Comment

Designing circuit boards with DDR3? Full-day, hands-on tutorial in Europe shows you how. Munich, May 14

System designs employing DDR3 SDRAMs present many new pcb design challenges compared to DDR2. DDR3 clock, address, and control lines employ a new fly-by topology; setup and hold times need to be just right because there are reduced timing margins thanks to the higher DDR3 clock speeds. If you are facing the challenge of designing a pcb populated with DDR3 SDRAM DIMMs, you need not face that challenge alone. You can take a full 1-day workshop that will successfully lead you through the complex design maze and help you reach the end of the maze with a pcb that works.

The one-day workshop is part of CDNLive! EMEA taking place in Munich on May 14-16. The full-day DDR3 pcb design workshop takes place on Monday, May 14. Seating is limited, so you will want to register now before all the seats are gone.

Register here.

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Spansion CEO maps divergent semiconductor memory strategy at Globalpress—a destiny that leads to smart memory

Spansion CEO John Kispert mapped out an individualized product strategy for the semiconductor memory vendor at today’s Globalpress Electronics Summit being held this week in Santa Cruz, California. Kispert first pointed out that Spansion currently has approximately 8000 customers who have designed Spansion semiconductor memory into more than 100,000 end products in a very wide cross section of the electronics business. “Each customer gives us a little glimpse of the next two to three years in the electronics industry,” he said. Together, those glimpses have gelled into a strategy that’s clearly intended to keep Spansion apart from the semiconductor vendors competing for the commodity semiconductor memory business.

Kispert’s presentation focused on the growing importance of a product’s user interface. Over the last few decades, there has been quite an evolution in user interfaces and Kispert mentioned two. The first example is the mobile telephone handset. In the 1990s, the user interface was little more than a keypad and a 1-line LED display or a simple monochrome LCD. Eventually, the single-line displays gave way to more complex, full-color, graphical LCDs but the keypad remained the primary user input device until Apple upset the—er—apple cart with the iPhone. Suddenly, every phone needed a large, graphical LCD with a touch-screen interface.

The second example was video games. In the 1970s, said Kispert, we had Atari Pong. The user interface consisted of two single-turn potentiometers and a black-and-white CRT with blocky graphics. Thirty years later came the Microsoft Kinect and the Nintendo Wii, with user interfaces based on gesture recognition and full-body movement.

In both cases, the memory capacity and bandwidth requirements have climbed with the increasing complexity of the user interface. Kispert predicted that trend would continue, with the next step being far more capable voice recognition. “Spansion is spending a lot of high-end talent on developing support” for speech-based user interfaces, he said. That’s in contrast to other semiconductor memory vendors who are ramping development of more advanced, high-density NAND Flash technologies for commodity markets—the SSD market in particular.

Voice recognition requires dedicated local hardware (processor and memory) to deliver a speech-based user interface that’s sufficiently accurate and that responds quickly claimed Kispert. It’s a technology problem that will take about three years to solve, he predicted, and then he stated that Spansion was working with Nuance as a partner on advanced speech-recognition technology.

Where might this technology be used? Kispert gave one example, a venue already experimenting with speech recognition: the automotive segment. Cars are becoming smart computers on wheels and voice recognition, as well as facial and gesture recognition, seem destined to replace many manual controls currently found in cars. It’s much safer to use a gesture to adjust radio volume than to reach over and grope for a volume-control knob on the dashboard said Kispert.

Gesture and face recognition may well find their ways into other products where no such recognition is currently used, he added. For example a television might use facial recognition to recognize a user who only looks at three channels (Dad) as opposed to teenage users who frequently view as many as 45 channels. Why offer up unused channels if you can recognize the person using the TV right now? Why not simplify the choices when possible?

This future as described by Kispert contained a surprise at the end. In three to five years, Spansion plans to be adding controllers and software to its memory technology to create complete semiconductor solutions to the problems associated with interfacing to users. Many academics have predicted the advent of smart memory. Now the CEO of Spansion has indicated that he too sees a future there and he’s taking Spansion towards that goal.

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Lexar translates USB 3.0 specs into significant benefits that consumers care about with the new S73 JumpDrive

Sometimes, we insiders get pretty esoteric in the way we describe technological improvements. Take SuperSpeed USB 3.0 for example. Most consumers know it’s faster than USB 2.0—after all, 3.0 is bigger than 2.0 so it must be better—but perhaps they don’t know how much faster. And really, they don’t care that much about 0.5Gbps versus 5Gbps because that’s pretty ethereal. It doesn’t really tell you what you’ll get in real world activities.

Lexar apparently understands. The company’s recent email newsletter for its latest USB 3.0 S73 JumpDrive has this clear explanation:

“You’ve got better things to do with your time than waiting for your files to transfer. With the new Lexar JumpDrive S73 USB 3.0 flash drive, you can transfer files faster—like a 3GB HD video clip in less than 2 minutes. Compared to the nearly 20 minutes it would take using a standard USB 2.0 drive, that’s a huge time savings.”

We can all identify with that, I think. I know I’ve sat, waiting for that little red LED on my USB drive to stop blinking so I could pull the drive and get on with the day.

Following up on a link associated with the Lexar S73 JumpDrive, I found this closely related video about capturing digital images. The video includes a consumer-friendly discussion of the concepts of the NAND Flash controller and the link between the number of NAND Flash “lanes” and write speed. Here is is:

The Lexar S73 JumpDrives are available in capacities from 8 to 64Gbytes and read/write speeds to 45/20 Mbytes/sec. Of course, the speed depends on the JumpDrive’s internal NAND Flash storage controller and the number of NAND Flash chips available.

Although the Lexar video actually discusses SD cards, the same concepts apply to the design of controller chips for USB storage drives and for SSDs. Performance depends on the NAND Flash storage controller and the number of lanes to NAND Flash devices in either case.

For more information on advanced NAND Flash storage controller design, click here.

Posted in Flash, NAND, ONFI, USB | Leave a comment

BIWIN America introduces 12x20mm e-MMC SSDs with on-chip controller, power-on boot, explicit sleep mode

BIWIN America has just announced a “single-chip” SSD device employing the e-MMC interface. The device is available in capacities from 2 to 64Gbytes, all packed into a 169-ball BGA package measuring 12x20x1mm. An integral SSD controller provides built-in BCH error correction, wear leveling, and bad-block management. A power-on boot feature allows an embedded host CPU to access boot code without an upper-level software driver and an explicit sleep command allows the host controller to take direct control of the SSD’s sleep mode to improve system power efficiency. These new BIWIN SSDs are based on MLC (multi-level cell) NAND Flash devices and run on 1.8 or 3.3V.

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Low-cost Intel 330 series SSDs sport SandForce SF-2281 SSD Controller

According to this extremely informative article on the Anandtech.com site, Intel’s just-released 330 series SSDs push Intel into the low-cost SSD zone using the SandForce SF-2281 SSD controller. Apparently, Intel’s 520 SSD series also employs this controller, but the use of 25nm MLC (multi-level cell) NAND Flash with lower endurance permits Intel to drop the warranty period from 5 years (for the 520 SSD series) to 3 years for the 330 SSD series. The price for the Intel 330 SSD series in three available capacities—60, 120, and 180Gbytes—is $89, $149, and $234 respectively.

Posted in Flash, NAND, SSD, Storage | Tagged , , , , , , , | 1 Comment

Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?

Multicore SoC and processor designs were our solution to the death of Dennard Scaling when IC process geometries dropped below 90nm, when processor speeds hit 3GHz, and when processor power consumption went off the charts. Since 2004, we’ve transformed Moore’s Law into a processor-core replicator, spending transistors on more processor cores rather than bigger, smarter, faster processor cores. But there’s a storm brewing once more, heralded by the dismal utilization of supercomputers that run hundreds to hundreds of thousands of processors in parallel. Currently, per-core processor utilization in supercomputers is less than 10% and falling due to memory and I/O limitations. If we don’t want the same thing to happen to our multicore SoC designs, we need to find a new path that allows processor utilization to scale along with processor core count.

That’s how Samplify CTO and founder Al Wegener opened last week’s presentation to the Santa Clara Chapter of the IEEE Computer Society. Wegener’s company specializes in data compression, which happens to be a way to get more bandwidth out of your existing memory and memory interfaces. But before he cranked up his memory-compression sales pitch, Wegener covered a lot of useful ground that every SoC designer needs to know.

The bedrock foundation of any processor-memory discussion is the memory hierarchy and Wegener provided this handy chart:

At the bottom, left of the chart is the fastest memory available to processors: registers. Now registers may not seem to be much like memory but they are. Registers are simply very fast memory locations with unique instruction-access modes. Processors need and have multiport access to registers so that different parts of the processor’s execution pipeline have unimpeded access to register contents. The number or processor registers has grown over the years from seven 8-bit registers in the Intel 8008…the first second commercial microprocessor…to dozens of 32-bit general-purpose and wide specialized registers in today’s 32- and 64-bit processor cores. However fast, multiport access to all of these registers comes at a steep price in terms of silicon area and routing congestion, so the number of processor registers is inherently limited.

That’s why there’s cache. Cache-memory access is almost as fast as register access, but you can have a lot of cache memory—comparatively. L1 caches typically have 32 or 64Kbyte capacities and often there are independent caches for instructions and data. Caches take a huge load off main memory, relieving the pressure to speed up main-memory access.

To a point.

Large data sets can easily outgrow L1 caches, which are size-limited because they must be as fast as the processor core. That’s why there are L2 caches. That’s also why there are L3 caches. Each step up the cache hierarchy is bigger—and slower. Finally, you get to main memory, which seems to be missing from Wegener’s chart but I can assure you it’s there. Main memory is usually implemented with SDRAM these days and today’s DDR SDRAM memories need hundreds of processor clock cycles to respond to memory transaction requests, so you really need caches. That’s just the way processor-based system design has evolved. Everyone would really love DRAMs that ran as fast as processor cores. Not yet.

Once you get beyond caches, you generally need to go off chip. That’s where the fun begins. The Intel 8008 microprocessor came in an 18-pin package and ran off a 740KHz clock. All memory was off chip (no cache) and the processor’s instructions executed in 10 to 22 clock cycles. At that time, the memory wall was very far away. The wall got closer each time processors got faster and wider.

Today, multicore processor designs have a voracious appetite for memory bandwidth and we’ve taken several steps to feed that appetitie.

The first step we’ve taken is to add pins so that we can connect wider memory arrays to the processor. Here’s a chart showing the historic rise in the number of pins for Intel x86 processors.

The chart shows the handful of pins needed by the Pentium III in 2000 to more than 2000 pins for the 6-processor Intel Core i7-3960x in 2011. (I think Wegener’s graph has swapped the red and blue curve colors. The red curve seems to match the bandwidth scale and the blue curve seems to match the pin count scale.)

You can’t miss the memory-bandwidth jump from 2007 to 2008 as the effect of having four or more processor cores took effect. Multicore architectures have a big problem with memory bandwidth.

Lest you get the impression that this problem only afflicts Intel CPUs, or even CPUs in general, take a look at this chart, which shows the drop in per-core PCIe and GDDR SDRAM bandwidth as the number of cores in Nvidia GPUs has increased:

GPUs are walled in as well.

The next steps taken to overcome the memory wall included faster memory-I/O pins (the rising clock rate of SDRAMs from SDR to DDR 2/3/4, for example), more cache to relieve the pressure on main memory, and 3D IC assembly permitting many hundreds of memory-dedicated I/O pins (as with Wide-I/O DRAM). The ultimate attempt may be optical interconnect, abandoning electron-based interconnects completely.

Wegener’s approach, through Samplify, is to compress the data so you don’t need to move as many bits between the processors and memory. Hence the Samplify slogan: “…simply the bits that matter.” Wegener’s argument is pretty simple. Assume, for example, you could compress the data stream by 2x, removing half of the bits from the memory stream. That’s the same thing as doubling the existing memory bandwidth, which is like doubling the DDR data rate once again or doubling the width of the memory interface. What’s it cost to do that? About 100K gates says Wegener. At current lithographies, that fits under a bond pad, he adds.

The 100K gates are used to construct a hardware data compressor with three performance levels: lossless, fixed-ratio or fixed-rate (settable in steps of 0.05), and fixed-quality (settable in steps of 0.05 dB). You crank the setting up until it starts to hurt, then back off one click.

Now before you go ballistic about lossy compression, consider some really interesting facts. A lot of data comes from real-world transducers and A/D converters that capture anywhere from 8 to 20 bits of real data. (OK, 24 bits if you’ve got a really expensive converter.) These data samples tend to get stuck in 32-bit locations with anywhere from 12 to 24 irrelevant bits per sample (likely zeroes). You don’t really want to spend precious memory bandwidth or consume power to ship around a bunch of zeroes that will vaporize upon arrival. It’s easy to see that lossy compression applied to these data samples could drop a lot of bits but lose not a single significant bit (…simply the bits that matter).

Need more proof? What do you think you’ve been listening to for the last 10 years? Compressed music and VOIP phone calls. What have you been watching for the past 5 years? Compressed video.

Does compression really work in more than just these situations? Go ask Samplify. Wegener made me a believer.

Posted in 3D, DDR, DDR3, DDR4, DRAM, Flash, PCIe, Wide I/O | Tagged , , , | 9 Comments

DDR4 DIMM and SO-DIMM interposer modules work with Agilent logic analyzers

FuturePlus Systems has announced a pair of DDR4 SDRAM interposer modules compatible with Agilent logic analyzers to aid in hardware debugging of DDR4-based memory systems. The FS2501 interposer module  works with DDR4 DIMMs at transfer rates to 2133Mtransfer/sec and the FS2502 interposer module summary.html works with DDR4 SO-DIMMs at transfer rates to 1600Mtransfer/sec. Both modules provide a mechanical, electrical, and software interface between an Agilent logic analyzer and the DDR4 memory socket. The modules have built-in terminations and include Protocol Decoder software and configuration files for Agilent logic analyzers.

FuturePlus FS2501 DDR4 DIMM Interposer Module for Agilent logic analyzers

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A detailed look at the IP components of an SSD controller chip by Dr. Eric Esteve

IPNEST blogger and analyst Dr. Eric Esteve has just published a detailed look at many of the IP components needed to design a high-performance SSD controller chip including a NAND Flash controller and high-speed PHY interface for NAND Flash devices. These IP types pave the way for the emerging NVMe interface specification, which Esteve expects to be used in data centers to support cloud computing and in mobile products such as PCs and tablets.

His article on the SemiWiki site is here.

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Intel jumps on the PCIe SSD bandwagon with the fast, new 910 Series

Intel has just announced an SSD family based on the PCIe expansion-card form factor and interface. The SSD family is called the 910 Series and it’s based on Intel High Endurance Technology and MLC (multi-level cell) 25nm NAND flash memory that allows up to 10 full drive writes a day for 5 years. Intel’s press release says that’s a 30x endurance improvement over its standard MLC-based flash products. The result is an SSD with a 5-year warranty. The 400Gbyte version of the Intel SSD 910 Series costs $1,929 and the 800Gbyte version costs $3,859.

According to this article on the Anandtech.com site, the Intel 910 Series uses an 8-lane PCIe 2.0 implementation (with a raw PCIe bandwidth of 4Gbytes/sec in each direction). The rated peak sequential read/write performance for the PCIe-based 910 Series SSDs is 2000/1000 and 1000/750Mbytes/sec respectively for the 800 and 400Gbyte family members and the peak random read/write performance is 180/75K IOPS for and 90/38K IOPS respectively for the 800 and 400Gbyte family members.

Also according to the Anandtech article, the Intel 910 SSD Series employs either two or four SSD controller ASICs with dual-core processors. One processor core handles the ONFI 2.0 interface to the NAND Flash devices and the other processor core handles the “SAS interface.”

What’s that? Isn’t the Intel 910 SSD Series based on PCIe? Yes, it is but there’s apparently a PCIe-to-SAS bridge connected to that PCIe connector.

And here’s a photo of the product:

Posted in Flash, NAND, ONFI, PCIe, SAS, SSD | Tagged , , , , , | 1 Comment

Micron’s mSATA RealSSD C400 and RealSSD C400v drives get huge performance from their SATA 6Gbps interfaces and 25nm MLC NAND

Micron’s new RealSSD C400v and RealSSD C400 mSATA SSDs can operate as SSDs in ultralight, ultrathin notebooks and can also be used as a Flash caches in SSD/HDD hybrid systems. The drive fits the 3×5 cm, 3.75mm-thick mSATA form factor and sports a 6Gbps SATA interface. The drives are available in capacities ranging from 32 to 256Gbytes, based on the use of Micron’s 25nm MLC (multi-level cell) NAND Flash devices. The Micron image on the right shows that the drives are based on a Marvell 88SS9174-BLD2 SSD controller chip—the same SSD controller that Micron used in its Crucial RealSSD C300 drives introduced in 2010. (See “AnandTech analyzes Crucial C300 SSD with Marvell controller in “The SSD Diaries.” You must read these conclusions.”)

The new drive’s performance specs impress:

  • Sequential read speed: As much as 500 Mbytes/sec, depending on drive capacity
  • Sequential write speed: From 50 to 260 Mbytes/sec depending on drive capacity
  • Active power consumption: Less than 150mW (32 and 64 Gbyte capacities), less than 200mW (128 and 256 Gbyte capacities)
  • Idle power consumption: Less than 65mW (32 and 64 Gbyte capacities), less than 85mW (128 and 256 Gbyte capacities)
Posted in Flash, Micron, mSATA, SSD | Tagged , , , , , , | Leave a comment

A possible roadmap for Wide I/O that leads to 2Tbps of SDRAM memory bandwidth—per device

Cadence Product Marketing Director Marc Greenberg—one of the speakers at last week’s EDPS conference held in Monterey, California—spoke about why the Wide I/O SDRAM is probably the “killer app” that unleashes 3D IC assembly into the mainstream. Richard Goering has already written a blog about most of Marc’s talk (see “EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs”) leaving me with little to add but a discussion of a potential Wide I/O roadmap that leads from the present JEDEC standard that delivers 100Gbps of memory bandwidth through a 512-bit interface running at 200M transfers/sec to 2Tbps in the future. (It’s actually four 128-bit data interfaces operating in parallel.)

Now Marc carefully pointed out that he was not representing JEDEC during his talk, so the following graphic is not an official roadmap. Nevertheless, here’s a potential roadmap for the Wide I/O 3D technology:

If you look at this graph, you might first wonder why the current Wide I/O standard is so slow. Single-data-rate transfers at 200M transfers/sec extract “only” 1Gbps of bandwidth from the Wide I/O data interface. The all-too-simple answer is “power.” The current JESD229 Wide I/O Single Data Rate (SDR) JEDEC standard was designed to deliver twice the bandwidth of LPDDR2 memory at the same operating power specifically for power-constrained mobile applications. (See “3D Week: JEDEC Wide I/O Memory spec cleared for use”.)

Obviously, advanced semiconductor memory process technology can go faster than 200MHz, single data rate. It already does for several SDRAM device classes including DDR2, DDR3, DDR4, and LPDDR2/3. So Greenberg’s graph, reproduced above, states the less-than-shocking news that Wide I/O SDRAM transfer rates could (likely will) increase and could adopt the well-accepted double-data-rate transfer mechanism—at the expense of operating power.

The above timeline shows the first step up in transfer rate might be to use a 266MHz transfer clock resulting in 532M transfers/sec using DDR signaling, nearly tripling the bandwidth to 266Gbps. It’s also possible to consider bumping the transfer rate to 2133M transfer/sec using a 1066MHz clock—still well within the speed envelope of today’s semiconductor memory processes. Further into the future, the rate could again jump to 2Tbps.

What’s amazing is that these transfer rates are all for individual devices.

What’s even more amazing is that we will certainly figure out something interesting and exciting to do with this extra bandwidth.

Posted in DDR, DDR3, DDR4, DRAM, SDRAM, Wide I/O | Tagged , , , , | 2 Comments

4th International Memory Workshop in Milan tackles all things non-volatile with respect to semiconductor memory. May 20-23

You will need to travel to Milan, Italy to attend the 4-day intensive event devoted to non-volatile memory, which seems to be the exclusive topic for the 4th International Memory Workshop Symposia on VLSI Technology and Circuits covers latest STT-MRAM developments  being held on May 20-24. The event starts on Sunday with a morning tutorial on system-memory interactions followed by an afternoon tutorial on Magnetic RAM (MRAM). The sessions held on Monday, Tuesday, and Wednesday cover 2D and 3D NAND Flash memory, Resistive RAM (RRAM), MRAM, ferroelectric memory (FRAM), nanocrystal memory, graphene-based memory, phase-change memory (PRAM or PCM), and even stranger storage physics. There’s also a lonely single session on DRAM. From the program, it appears that you should become an expert in all aspects of non-volatile memory—should you survive the entire event.

More info here.

Posted in DRAM, Flash, Memristor, MRAM, NAND, ReRAM, Storage | Tagged , , , , | Leave a comment

Symposia on VLSI Technology and Circuits covers latest STT-MRAM developments

Session 7 of the 2012 Symposia on VLSI Technology and Circuits is all about Spin-Torque-Transfer Magnetic RAM (STT-MRAM), one of the several technologies hoping to challenge NAND Flash memory for the top spot in the non-volatile memory hierarchy. Five presentations are scheduled from Grandis, LEAP, NEC, Renesas, Tohoku University, Kyoto University, and KAIT. The event takes place from June 12-15 in Honolulu, Hawaii. Session 7 takes place on June 12.

Posted in Flash, MRAM, NAND | Tagged , , | Leave a comment

Want to tour the Kingston SSD factory with TweakTown?

Kingston Technology manufactures SSDs in Taiwan’s Hsin Chu Science Park and TweakTown’s Cameron Wilmot recently went for a visit. With his camera. Although Wilmot wasn’t allowed to shoot video, he did shoot a lot of photos that are included in his lengthy report. Wilmot’s images show a large and fairly familiar set of surface-mount manufacturing machinery, which is exactly what you’d expect to see in an SSD factory. If you’ve not visited such a facility or if you just want to see how Kingston does it, now’s your chance.

Click here.

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Interview with Whiptail’s CTO James Candelaria demonstrates how SSD controllers can greatly improve NAND Flash endurance by managing write amplification

As NAND Flash geometries continue to shrink, device endurance specs have suffered, which is a significant challenge when using these devices in SSDs. This interview with Whiptail’s CTO James Candelaria discusses how his company’s approach to buffering writes in SSD RAID arrays reduces the effects of write amplification, thus preserving the native device endurance available. Good reading for anyone designing SSDs or SSD controllers.

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Need fast, low-power, small, dual-ported embedded SRAM for your SoC designs? Memoir Systems Renaissance 2X memory compiler lets you pick all three: power, performance, and area

SoC designers use a lot of on-chip dual-ported SRAM, typically as an interface buffer between two major logic blocks. IP startup Memoir Systems has just introduced four memory compilers that produce a range of dual-ported embedded SRAM blocks and these memory blocks outperform conventional dual-port SRAM IP blocks in terms of power, area, and speed. That’s right, you get to pick “all of the above” for your dual-port RAM requirements. The trick here is to use existing, proven single-port memories generated by “industry standard” memory compilers and then stitch these memories together with logic to produce what Memoir calls “algorithmic memory” as shown in this graphic:

The diagram shows several standard single-port SRAM arrays (labeled “1P,” with 12 such 1P blocks shown in this example) surrounded by Memoir’s algorithmic memory logic to form one large dual-ported SRAM block. In this case, the diagram shows two independent memory ports leading into and out of the memory block, making this design a full dual-ported SRAM.

This approach obviously adds overhead—about 15% for the algorithmic memory logic and the duplicated address decoders and data multiplexers. However, that 15% overhead is on top of the area needed by the single-port SRAM blocks. Compared to existing dual-port SRAM designs, Memoir Systems’ approach saves area. How much? Take a look at this chart:

The top curve in this chart shows memory density for single-port SRAM based on a 6T (six-transistor) memory cell. The bottom curve shows memory density for dual-port SRAM based on an 8T memory cell, which is typical of dual-port SRAM IP. For a variety of reasons, the bit density for conventional dual-ported SRAMs is about half that of single-ported SRAMs. The middle two curves show the range of densities you get from the four different Memoir Systems Renaissance 2X memory generators. These densities are closer to those for single-ported SRAMs than for conventional dual-ported SRAMs.

Why four memory generators? Each of the four generators provides a different type of dual-ported memory so that you can trade off capability versus area and speed. The four generator types produce:

  • Full dual-ported memory (two ports, each with read/write capability)
  • Dual-ported memory with one read and one write port (for unidirectional buffers)
  • Dual-ported memory with one read/write and one write port
  • Dual ported memory that can perform two simultaneous reads or one write

The Memoir Renaissance 2X memory generators use existing “industry standard” single-ported memory cells available from other IP vendors and then stitch these cells into a logic matrix created by the Memoir memory generators. The result is an IP block that presents two SRAM interfaces to the other logic on the SoC.

So how real are the claims of better area, power, and speed. Glad you asked. Here are the curves:

This chart shows you the area savings relative to a conventional dual-port SRAM IP design. As you can see from the curve, a full dual-ported memory using the Memoir algorithmic memory generator is not area competitive with conventional dual-ported SRAM with memory capacities below about 300Kbits. However, by the time you reach a couple of Mbits in capacity, you are better off to go with the Memoir approach in terms of area. But this is where the other flavors of dual-ported SRAM come into play. If you don’t need for both ports to be full read/write ports, then you are always better off—in terms of area—with the Memoir algorithmic memory approach as shown by the other curves in the chart.

How about power consumption? Here’s the curve:

The top curve is for conventional dual-ported memory. Note the knee in the power curve at 400MHz for conventional dual-ported memory. Now note that there are no such knees for the Memoir algorithmic memory. Based on this one data point (1Mbit dual-ported memory implemented in 40nm), it appears that you are virtually always better off from a power-consumption perspective using the algorithmic memory over conventional dual-ported memory.

Finally, here’s the clincher from my perspective:

This chart plots memory speed versus area for a 1Mbit dual-ported memory implemented in a 40nm process technology. Note that the conventional dual-ported SRAM starts to need a lot more area at 400MHz, which explains the steep rise in power at 400MHz shown in the previous chart. Also note that the conventional dual-port memory tops out at about 500MHz. It can’t go faster. However, Memoir Systems’ algorithmic memory, which is built from conventional single-ported SRAM blocks, extends the operating range of dual-ported memory to 700MHz (again assuming 40nm). There are a lot of SoC designs that need that extra speed. Perhaps yours is one of them.

So you can indeed get advantages in power, area, and performance from this technology.

One final note: This announcement from Memoir Systems discusses four 2-port memory-block generators in the company’s Renaissance 2X family. However, the technology is not limited to creating dual-ported memories. On a consulting basis, Memoir Systems has already been working with clients on creating memory IP blocks with as many as eight ports.

Posted in SRAM | Tagged , , | Leave a comment

Free 2-day SSD Summit already started. Today’s the last day. Click here now, quick.

Yesterday, Avnet Embedded opened an online SSD Summit with a ton of free info. The trouble is, I just found out about it and it ends today. I count eight technical Webinars to watch and seven live chat sessions on Wednesday. Go there now, or miss the education. Click here.

Posted in SSD, Storage | Leave a comment

Supertalent USB 3 SSD memory-stick drive virtually “saturates” USB 2 port using 8-channel LSI SandForce SSD controller

In a sea of undifferentiated USB memory sticks, Supertalent is coming on very strong by differentiating its USB 3.0 Express RC8 drive  through its use of an LSI SandForce SSD controller with 8 channels of NAND Flash memory.

As a result of using so many memory channels, the drive provides significantly more small-block transfer performance than other USB 3.0 drives, as shown in this graph:

But the really surprising bit of information is the way the 8-channel SSD implementation can almost completely saturate a USB 2.0 port. According to Supertalent, the theoretical maximum data throughput for a USB 2 port is 44 Mbytes/sec for reads and 38 Mbytes/sec for writes. In 4Kbyte random-access tests, the Supertalent USB 3.0 Express RC8 drive achieves 39 Mbytes/sec for reads and 38 Mbytes/sec for writes. That’s 89% bus saturation for reads and 100% saturation for writes.

Here’s a somewhat over-the-top video from Supertalent that explains all of this (with enough hard data to make it worthwhile):

Posted in Flash, NAND, SSD, USB | Leave a comment

Forbes.com publishes article on growth areas for SSDs and NAND Flash devices: mobile and cloud

Tom Coughlin, the President and founder of Coughlin Associates, has just published a good background piece on growth paths for SSDs and Flash memory. I commend it to your attention and I particularly want to call your attention to several strong statements.

Coughlin writes:

“Currently even the lowest price SSDs sell for about $0.70/Gbyte while the most price impacted HDDs sell for $0.14/Gbyte (a difference of 5:1).  As the available production volume for HDDs recovers the price of HDDs in real dollars will continue to fall.  In addition if higher areal density HDDs are introduced later this year, capacity prices will drop to pennies per GB while the least expensive SSDs will likely drop to $0.50/Gbyte by the end of 2012.  Economics is an important consideration for consumer and business purchases, and price does matter.”

So if you’re expecting the price-per-Gbyte of SSDs to reach parity with HDDs any time soon, please stop holding your breath. Although many pundits predict such an event, the experts I follow such as Coughlin and Jim Handy continue to look at historic trends and write “’Taint so.” (See “SSD and HDD Economic Forecast: Analyst Jim Handy Speaks Out” in the Denali Memory Report for a historic view from two years ago.)

Coughlin continues:

“Over the next year or two there will be additional consumer and business products that shift from using HDDs to only using SSDs or flash memory. In mobile devices and automobile applications the ruggedness of flash memory and its ability to be put into smaller volumes than HDDs provide other advantages to users even if the purchase price is greater.  In addition, many mobile applications have limited local storage (to control the product price) and depend upon storage and other resources from “the cloud.”  Mobile consumer electronics will be a major growth area for flash memory, but likely not as much for traditional SSDs.”

Here, Coughlin is pointing out that HDDs have an inherent cost floor below which they cannot go. In the Denali Memory Report article referenced above, Jim Handy noted that HDD costs seemed to have bottomed out at $50, leaving a vast unserved market for devices that need less costly storage.

Coughlin then points out other areas for SSD and Flash growth:

“The growth areas for SSDs will primarily be in two areas.  In client computing applications, such as Ultrabooks, SSDs will be used alone in the most expensive machines while less expensive Ultrabooks will use a combination of a HDD and an SSD, or else flash memory cache in the HDD (a hybrid HDD), or possibly on the motherboard (although this seems less likely)…

The other growth area for SSDs is in enterprise applications where SSDs can provide fast transaction processing, partly to support cloud services and storage in the cloud.”

See the Forbes.com site for the complete article.

Posted in Flash, HDD, SSD | Tagged , , , , , | Leave a comment

50-company PCIe SSD task force takes on interoperability issues with PCIe-connected SSDs

PCIe interfaces give SSDs are real performance boost. It’s easy to scale that performance immediately by adding PCIe lanes—unlike the SAS and SATA disk-interface specs, SSD vendors need not wait for the next, faster release of the PCIe spec to go faster. However, server and PC hosts don’t yet automatically see PCIe-attached SSDs as storage devices and so vendors must offer drivers to fill the gap. Not all drivers are created equal, which complicates matters for system integrators.

The Solid-State Storage Initiative technical group, part of SNIA (the Storage Networking Industry Association), plans to alleviate this potential interoperability problem. A task force has been set up to address these incompatibility challenges. Task force member companies include a collection of the leading drive and system vendors:

  • Agilent
  • Allion
  • Apacer
  • Calypso
  • Cisco
  • CLabs
  • Corsair
  • Coughlin Associates
  • Dell
  • eTron
  • Fusion-io
  • HDS
  • HP
  • HGST
  • Huawei
  • Intel
  • Lecroy
  • Lenovo
  • Lotes
  • LSI
  • Marvell
  • Micron
  • Molex
  • Mushkin
  • Objective Analysis
  • OCZ
  • Oracle
  • Phison
  • Renesas
  • Samsung
  • SanDisk
  • Seagate
  • SMART Storage
  • STEC
  • Taejin
  • Tektronix
  • TMS
  • Toshiba
  • Tyco
  • Unigen
  • Viking
  • Virident
  • Western Digital
Posted in PCIe, SAS, SATA, SSD | Tagged , , , , | 1 Comment

LSI Corp releases multiple PCIe SSD and Flash-cached RAID storage cards in Nytro portfolio

LSI Corp has just announced a number of products in its Nytro line of PCIe-based storage cards. The LSI Nytro WarpDrive is a second-generation SSD card available in capacities of 200Gbytes to 3.2Tbytes using a memory-stacking architecture to load the card with MLC or SLC NAND Flash devices. The Nytro WarpDrive employs the company’s SandForce Flash storage processors and SAS controllers. According to the press release, one LSI Nytro WarpDrive delivers the I/O performance of hundreds of HDDs while consuming far less power and requiring far less space in a rack server. Cooling requirements are also reduced, of course.

LSI Nytro WarpDrive SSD PCIe card

The LSI Nytro MegaRAID Application Accelerator Cards are HDD RAID controllers with integral NAND Flash caching. These cards automatically shuttle data between the on-board Flash and the HDDs to extract significantly more performance from RAID arrays.

LSI Nytro MegaRAID Flash-cached RAID PCIe card

Posted in Flash, HDD, PCIe, SAS, SSD | Tagged , , , , , | Leave a comment

Free Webinar on essential memory and storage verification IP: DDR3/4, LRDIMM, 12Gbps SAS, NVMe, Ethernet. April 10.

Verification IP (VIP) is an essential component of the development process for all ICs and systems and now you have the chance to listen to a free April 10 Webinar on applying that essential component in memory and storage applications. The VIP components being discussed include:

  • DDR3/4
  • 12Gbps SAS
  • NVMe
  • Ethernet

Once more, the Webinar is free. More info here.

Posted in DDR, DDR3, DDR4, DRAM, Ethernet, Flash, LRDIMM, NVM Express, NVMe, SAS | Tagged , , , , , | Leave a comment

Want some additional details about the Micron Hybrid Memory Cube?

This week at Design West (the conference previously known as the Embedded Systems Conference), I had a chance to speak with Mike Black from Micron about the Hybrid Memory Cube (HMC), a 3D DRAM assembly aimed at high-performance computing. The first thing he told me was that Micron had built an operational prototype of the HMC. It delivers 121Gbytes/sec of bandwidth, about 95% of the target bandwidth: 128Gbytes/sec. He promised to send me a photo, but it looks like a prototype not a finished product so Micron has not been eager to pass the image around.

The HMC is based on a 5-die 3D stack. The top four die are DRAM (not SDRAM) die with the old RAS/CAS sort of arrangement. That’s so that Micron can build these DRAMs to run at the native RAM arrays speed. All of the DRAM control and I/O protocols are embodied in the bottom die, the fifth die, that’s currently made by HMC Consortium member IBM.

Black expects the first samples of HMC assemblies to appear in the first half of 2013. Based on DRAM litho roadmaps, he expects each of the DRAM die to have 4Gbit capacities by then. With four die, that means the sample HMCs in mid 2013 will have 16Gbit or 2Gbyte storage capacities. By 2015, Black expects that capacity to double as the DRAM chips reach 8Gbits per die.

The next step is to consider the link between the HMC and the host system. Currently this link is implemented as multiple high-speed differential serial channels. In the future, it might be an optical connection, which reminded me of the recently announced optical FPGA from Altera. That FPGA uses two 150Gbps MicroPOD optical transceivers from Avago for communications. After my meeting with Black, I went back into the Design West exhibit area where Altera was demonstrating that same optical FPGA. The Avago MicroPOD optical transceivers consume 2 or 3 Watts and can transmit signals for more than a few meters. (For more information, see “3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet”)

For more information about the HMC, see:

Note: Micron is presenting at the Electronic Process Design Symposium (EDPS) next week, on April 6. You now have less than a week to sign up for this event and if you have any interest in 3D IC assembly, then you need to be in Monterey on April 6.

More information about EDPS here.

Register for EDPS here.

Posted in 3D, DRAM, HMC, Hybrid Memory Cube | Tagged , , , , | Leave a comment

Micron releases video on using PCIe for fast, enterprise-class SSDs like its P320h SSD

As yet another example of how new, fast interfaces are changing the way SSDs fit into the enterprise storage arena, here’s a new video showing Gary Gentry, General Manager of Micron’s Enterprise SSD Division, explaining how and why Micron has integrated PCIe into its 2.5-inch, enterprise class P320h SSD.

PCIe and the coming NVMe specification are two examples of fast interfaces that are taking SSD performance to even higher levels by removing the interface bottleneck between the SSD and host systems. In Gentry’s words, this “turbocharges” the connection to the SSD.

The approach used by Micron in the P320h places the PCIe interface in the gap between the two connectors of the existing SAS/SATA port using some extra pins. To develop this drive, Micron developed its own NAND Flash controller and disk interface SoC. The company originally designed this controller SoC into a PCIe board that plugs into a server or PC PCIe slot. By adding a PCIe interface to the existing SAS/SATA port on the SSD, Micron’s P320h preserve’s the drive’s hot-swap and mechanical characteristics—so that it fits in with other enterprise-class HDDs from a mechanical perspective—while boosting I/O speed through the added PCIe port.

Posted in HDD, NAND, NVMe, PCIe, SAS, SATA, SSD | Tagged , , , , , , | Leave a comment

Cadence adds 12Gbps SAS and NVM Express verification IP to its VIP catalog

Today, Cadence announced the addition of two storage-oriented verification IP products: 12Gbps SAS and NVM Express (NVMe). SAS is currently the interface of choice for enterprise-class hard disk drives and 12Gbps is the next click on the interface-speed dial. NVMe is an adaptation of the PCIe interface specifically for solid-state disks. (See “Watch out SSDs, here comes the NVM Express!”) Both interface standards will become important in the cloud-centric future of the Internet and SoC designers are already thinking about chips that will employ one or both of these leading-edge standards.

For more information on the Cadence VIP catalog, clock here.

Posted in HDD, NVM Express, NVMe, SAS, SSD | Tagged , , , | 1 Comment

ISQED: Who and what will win the Universal Memory Derby?

Professor Cristophe Muller of Aix-Marseille University gave an excellent overview of non-volatile semiconductor memory as the third ISQED keynote this week. It’s a very good overview of today’s landscape and well worth discussing in a wider forum like this blog.

First, Professor Muller displayed this image, which gives a simple semiconductor memory taxonomy:

The simplest semiconductor memory split is between volatile memory (DRAM and SRAM) and non-volatile memory (everything else). Non-volatile memory then splits into memory based on charge storage (EEPROM, Flash, FRAM, and Silicon dots) and resistive memory. Now, I’m not sure about including FRAM in this first group, because FRAM stores data in the actual shape of ferroelectric crystal dipoles rather than in charge, but then I’m not a professor either. However, FRAM has been around for more than two decades and TI has been marketing relatively new versions of the very successful MSP430 microcontroller family with on-chip FRAM, including the recently announced and deliciously named low-power Wolverine line of “ultra-low power” MCUs. So there’s clearly life in FRAM.

Professor Muller has labeled the second type of non-volatile memory as “resistance switching” memory. To me, this is currently the most interesting category in the taxonomy because all of the would-be contenders for taking the crowns from Flash and DRAM are in this category, which includes MRAM, PCM, and RRAM (or ReRAM, or Memristor memory). This category includes a range of memory cells based on wildly varying physical phenomena.

Which brings us to a refinement in the taxonomy. Here’s the ITRS classification tree for non-volatile memory, as classified by technology:

On the left are the “baseline” technologies already in wide use: NAND and NOR Flash. Although FRAM appears in the ITRS “prototypical” category, it’s been shipping in low-capacity memory products for decades (I first wrote about FRAMs in the 1980s for EDN magazine and Ramtron announced an FRAM prototype at ISSCC in 1988). However, it’s certain that PCM (phase-change memory) and STT-MRAM (spin-torque-transfer magnetic RAM) are properly classified as prototypical. (See “Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC NV memory?”) Not shown here are earlier MRAM generations such as the products currently sold by Everspin, see “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit”.) These existing MRAM products are not prototypical; they’re shipping in the millions of units per year.

Finally, there are the “emerging” non-volatile memory technologies including Redox (reduction-oxidation, a form of resistive memory), nano-mechanical (nanoscale relays), molecular (using a variety of physical phenomena to store data), and FeFETs (FETs where the gate oxide is replaced with a non-volatile ferroelectric layer). As the name implies, the emerging non-volatile memory technologies are somewhat further out.

Although Professor Muller’s taxonomy classifies semiconductor memory as it exists today, none of these categories can yet meet his definition of the “universal memory,” which would in theory have the following characteristics:

  • Nanosecond read/write times
  • Gbytes of capacity
  • Infinite endurance (> 1015 write/erase cycles)
  • CMOS logic interface compatibility
  • Low power consumption (< 1pJ/bit) for read/write operations
  • Greater than 10-year data retention without power
  • Scalable with semiconductor process node advances

There’s currently no such animal as this universal memory, so system designers compromise on one or more of these characteristics depending on the application. NAND Flash memory is great for its low cost per bit and process scalability—it’s currently the semiconductor manufacturing industry’s lithographic process driver—but NAND Flash write times are relatively slow compared to DRAM and SRAM and NAND Flash data-retention time is falling with process-node enhancements as the number of electrons stored in each Flash memory cell drops with dimensional scaling (although this might change with 3D Flash structural advances). DRAM is great for speed and it’s pretty scalable with respect to process technology, but it’s volatile. Consequently, more than a few researchers and entrepreneurs sense that there’s an available niche—a chance to displace the current king and queen of semiconductor memory: NAND Flash and DRAM.

At the moment, there’s a large race in the resistance-RAM arena. Here’s a logo slide supplied by Professor Muller of just some of the entrants in the resistance-RAM derby:

The winner(s) of this derby may get the rights to displace DRAM and Flash memory, depending on how close the resulting devices come to achieving all of the characteristics of Professor Muller’s universal memory. The prize for this derby is worth millions of dollars per year and will soon be worth billions of dollars per year, as indicated in this slide:

The remainder of Professor Muller’s keynote speech focused on the three leading challengers in the non-volatile memory derby: MRAM, PCM, and RRAM. MRAM has the advantage of SRAM speeds, Flash data retention, and DRAM endurance. When and if STT MRAM comes to market, it could displace both the RAM/Flash combos and battery-backed RAM currently in use. Here’s a logo slide of some of the twenty or so companies in the MRAM race:

Note that Everspin on the left is currently far ahead of the others in commercializing MRAM, with millions of parts shipped. However, no company has yet announced STT MRAM parts, and STT MRAM is the type of MRAM that has a hope of reaching the bit densities of the current non-volatile memory king: NAND Flash.

PCM was off to an early start in this race. Numonyx was an early favorite to be the first to offer commercial PCM parts and Samsung announced a PCM device in May, 2010. (See “Samsung announces imminent release of a multichip module integrating DRAM and PCM for Smartphone applications”. ) However, there are technical hurdles with the chalcogenide alloys currently employed as the working material in PCM and not much has been heard from the PCM entrants lately. Certainly no new PCM product announcements have appeared in the past two years or so. Micron, a leading DRAM and Flash vendor, now owns Numonyx.

The big issue with PCM, said Professor Muller, is that the thermal-spike profiles needed to make the PCM chalcogenide alloys switch between the amorphous and crystalline states are somewhat difficult to control in practice. A fast, hot spike throws the material into the amorphous state by providing enough heat to liquefy some of the material and then quickly cooling the material, creating an amorphous solid. A slower, lower spike anneals the material into a solid crystalline state without entering the liquid state. The amorphous and crystalline states represent the two states of a binary bit. As you might expect, it takes some amount of energy to liquefy the alloy, making low-power operation somewhat challenging.

Professor Muller also mentioned the problem PCM devices have with  thermal annealing of the chalcogenide alloy by ambient temperature. As the device geometries scale with more advanced process nodes, it gets easier to anneal the bits out of a PCM device just from ambient temperature. Because of this, retention time becomes more of an issue with more advanced process nodes. Perhaps new structures or new materials might yet revamp PCM’s chances in the non-volatile memory derby.

Then there’s RRAM, ReRAM, and Memristors. HP put memristors on the memory map with the HP Labs announcement in 2008. Since then, HP announced a commercial memory partner for the technology—Hynix, a leading DRAM and Flash semiconductor memory vendor. Memristor memory is based on the creation and destruction of conductive filaments in a thin-film insulating layer usually made of some sort of metallic oxide. For example, HP’s memristor uses titanium oxide. One voltage causes the filaments to form by driving oxygen vacancies in the oxide, creating a conductive state. A higher or reverse voltage disrupts the filaments and reduces the conductivity. The binary bit is stored in the conductivity difference.

To date, there are no memristor-based parts on the market. The race is still being run.

It’s worth a bit of time to consider how Professor Muller sees these new memory technologies affecting system design. Here’s a very interesting slide that illustrates his thinking:

On the left is a highly simplified diagram showing how we partition systems today. There are large, identifiable blocks of cache SRAM and separate blocks of NOR Flash for code and NAND Flash for data. These days, the SRAM cache is usually on chip with the CPU and logic. For reasons of cost/bit, the NAND and NOR Flash memory is usually included in the system on separate, high-volume chips. With the right sort of memory—that is memory with characteristics that are closer to the ideal universal memory’s characteristics—memory could move to be more intimately connected to related blocks in the system. For example, multicore CPUs could have large blocks of non-volatile memory on the same chip and on-chip caches could become non-volatile. Heterogeneous memory hierarchies consisting of DRAM, NOR Flash, and NAND Flash could disappear. All of these changes would have a large influence on future processor-based system design.

However, all of these changes await the creation of a commercially viable non-volatile memory technology that can compete with DRAM and Flash. There are many entrants to this derby and it’s both exciting and interesting to watch as the race is run.

Posted in DRAM, Flash, Memristor, Micron, MRAM, NAND, NOR, ReRAM, SDRAM | Tagged , , , , , , , , , , , | 4 Comments

Where does LPDDR3 SDRAM fit in the low-power memory universe? How about Wide I/O SDRAM?

Marc Greenberg, Director of Product Marketing in the Cadence SoC Realization Design IP Group, just sent me some slides in connection with the recent introduction of the Cadence design and verification IP portfolio for LPDDR3 low-power SDRAM. I’ve already written a blog about the portfolio introduction (see “Upgrading your mobile or low-power SoC to LPDDR3? Got the right IP? You’ll need it to get maximum performance at minimum power”) but there are slides in Marc’s presentation that detail where LPDDR3 SDRAMs (and Wide I/O memory) fit in the low-power SDRAM universe and that’s information well worth discussing.

First, here’s a graphic showing you the SDRAM universe prior to the introduction of LPDDR2 SDRAM.

As you can see, this is a pretty messy universe. If you don’t need much memory and you don’t need much memory bandwidth, then parallel SRAM (PSRAM in the image) works for you. If you need moderate capacity and don’t need a lot of memory bandwidth, then low-power single-data-rate SDRAM might work. For larger memory capacities you will definitely want some form of DDR SDRAM because that’s how you get the most memory capacity for your money.

You have a lot of DDR choices including LPDDR1, DDR2, and DDR3 SDRAM. The above graphic helps a lot in selecting the right SDRAM technology based on desired system memory capacity and peak memory bandwidth. However, the introduction of LPDDR2 memory simplified this SDRAM universe quite a bit, as the following graphic illustrates:

You can see that if you want low-power SDRAM and you need any sort of capacity at any peak bandwidth up to 16 Gbits/sec, then 16-bit-wide LPDDR2 SDRAM is what you want at the moment. If you need more memory bandwidth, then you switch to (non-low-power) DDR memory or you use 32-bit-wide LPDDR2, as shown in this next image:

With 32-bit LPDDR2 SDRAM, you get all the way to a peak memory bandwidth of 32 Gbits/sec.

But today we’re entering the age of massively powerful mobile multicore processors such as the just introduced Samsung Exynos 5 Mobile Application Processor with two ARM Cortex-A15 CPUs cranking at 2GHz and a WXGA 3D graphics processor that drives a display at 60fps. These are very thirsty creatures and they crave memory bandwidth to process images, video, and audio. And don’t forget responsiveness when it comes to first-person-shooter twitch video games.

Now you’re talking about needing even more memory capacity and a lot more memory bandwidth. Now you’re talking about needing LPDDR3 SDRAM or even Wide I/O SDRAM.

This next graphic shows you where these newest SDRAM variants fit:

Both LPDDR3 (with two 32-bit channels) and Wide I/O memory can take your system beyond 100Gbits/sec in peak memory bandwidth, which is more than three times the bandwidth than shown in the previous image. The two different SDRAM technologies achieve this peak bandwidth in very different ways. As the name implies, Wide I/O SDRAM employs a very wide interface—512 bits—running at a leisurely 200MHz clock. LPDDR3 SDRAM cranks the clock to 800MHz and uses double-data-rate signaling to move 1600 Mbits/sec/pin. Your choice.

Nice to have choices.

Posted in DDR, DDR3, LPDDR, LPDDR2, LPDDR3, SDRAM, Wide I/O | Tagged , | 2 Comments

Upgrading your mobile or low-power SoC to LPDDR3? Got the right IP? You’ll need it to get maximum performance at minimum power

LPDDR3 is JEDEC’s next click on the low-power LPDDR SDRAM standard for mobile, portable, and other low-power devices. According to the JEDEC Web site, the LPDDR3 standard is still in development but the technical specs of the early devices announced by Elpida at the end of 2011 are impressive:

  • 6.4Gbytes/sec for one memory channel at 800MHz (twice the transfer rate of LPDDR2’s 3.2Gbytes/sec, when clocking at 400MHz)
  • Approximately 25% less power consumption

Samples of LPDDR3 SDRAMs have already shipped (see “Let’s start the new year with a bang! Elpida ships 4Gbit Wide I/O and LPDDR3 SDRAM samples”) so the time to start designing SoCs that will use LPDDR3 memory is already upon us.

To do that, you’ll need a variety of IP: an LPDDR3 memory controller, an LPDDR3 PHY, simulation models for these two pieces of design IP, LPDDR3 verification IP and LPDDR3 memory models, and your pc board designers would probably appreciate a design-in kit to help connect the resulting SoC to the high-speed LPDDR3 memory on the circuit board. All of these elements are available in the LPDDR3 IP portfolio announced today by Cadence.

Of particular note: the Cadence DDR Memory Controller has been upgraded to deal with the particular needs of LPDDR3 memory.

Cadence DDR Memory Controller Block Diagram

The upgrades to the Cadence DDR Memory Controller all relate to improving overall DDR memory bandwidth and latency and include:

  • Improvements to write-reordering and write-latency rules
  • Taking advantage of Additive Latency to streamline commands to the SDRAM
  • Tuning improvements to read/write command grouping
  • Traffic-based control of the SDRAM’s autoprecharge mode

It’s interesting to think about where these improvements to the DDR Memory Controller came from. Like all good design teams, the designers of the Cadence DDR Memory Controller learn from a close collaboration with their customers. SDRAM protocols have become extremely complex, so test cases with command sequences help to exercise many different controller scenarios based on traffic from the various data sources and sinks in the SoC. A bakers dozen of tough test cases supplied by a customer highlighted places where the design team could eke out even better bandwidth and latency performance from the DDR controller-SDRAM combination.

Good bandwidth performance got even better. Everyone using the DDR Memory Controller benefits.

Posted in DDR, JEDEC, LPDDR, LPDDR2, LPDDR3, SDRAM | Tagged , , , | 1 Comment

Memcon 2012 call for presentation submissions

Memcon 2012 will take place at the Santa Clara Convention Center in the heart of Silicon Valley on Tuesday, September 2012. This is the biggest conference in the world devoted to the use and manufacture of semiconductor memory (RAM, NAND and NOR Flash, more experimental memory technologies, etc.). It’s too early to register but not at all too early to submit a presentation proposal. We’re looking for cutting-edge presentations on all aspects of semiconductor memory design, manufacture, and use so if you’re associated with the semiconductor memory industry, you will want to present at Memcon 2012.

Why? Because hundreds of executives, technical thought leaders, engineers, press, and analysts will be sitting in the audience hanging on your every word. How do I know? That’s how is always is with Memcon.

You can get complete submission info on the call here.

The submission deadline is April 6. Time to jump on this opportunity. Like now!

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NVMe storage-optimized PCIe interface gets an Interoperability Lab at University of New Hampshire

The drive to adopt NVMe (a storage-optimized variant of the PCIe interface standard for SSDs) led by the NVMe Work Group now has an interoperability lab at the University of New Hampshire. The UNH-IOL—a “neutral, third-party laboratory dedicated to  testing data networking technologies through industry collaboration”—is developing an interoperability test suite for deliver mid year. The NVMe Work Group consists of more than 90 member companies including a core group of ten “promoters”: Cisco, Dell, EMC, IDT, Intel, Micron, NetApp, Oracle, SandForce (LSI), and STEC. With a promoter lineup like that, the future of the NVMe spec seems fairly well assured.

[NOTE] For more information on the NVMe interface, see “Why is the NVMe SSD interface inherently more efficient than disk-based protocols such as SATA?

Posted in NVM Express, NVMe, SSD | Tagged , , , , , , , , , , , , , | Leave a comment

Want to avoid losing more than half of your SDRAM’s bandwidth? The right SDRAM controller configuration can help prevent the loss. Just ask Vivante.

Graphics processors (GPUs) suck bits out of SDRAMs the way vampires do what comes naturally to them in the immensely popular Twilight book series by Stephenie Meyer. In other words, GPUs need all the memory bandwidth they can get and current SDRAMs can provide graphics subsystems with large amounts of memory at the lowest cost per bit and excellent bandwidth—but only if the memory controller has some understanding of the GPU’s specific memory-usage needs. That’s a design challenge Vivante faced when developing the ScalarMorphic Architecture for its latest line of multi-threaded, multi-core GPUs, which are designed into products ranging from smartphones to home-entertainment products.

The important thing to know about GPUs with respect to memory accesses is that the real-time nature of graphics applications requires that GPUs have a far more intense and intimate relationship with memory. There tend to be more memory clients at work within the GPU (perhaps five times more clients than for a general-purpose CPU) and these clients generate shorter bursts and more random accesses than general-purpose processors tend to generate. There are also more read/write conflicts and—specific to SDRAM accesses—more bank conflicts.

Here’s a graphic comparison of the number of memory clients in a CPU versus in a GPU, which clearly illustrates the difference:

The Vivante ScalarMorphic Architecture is a multi-core GPU design with multiple shaders, texture engines, rendering engines, and pixel engines in its 3D pipeline. There’s also a 2D pipeline and all of these elements can generate a variety of memory accesses. Here’s a block diagram of the ScalarMorphic Architecture:

Vivante’s approach to optimizing the GPU-SDRAM interface includes an “ultra-threaded” design (as many as 1000 threads per core) to increase tolerance for memory latency. Other optimizations include coalescing multiple memory requests to reduce the number of discrete memory accesses, maximizing data locality, and the use compression and caching to reduce memory-bandwidth needs. But it became clear to the designers at Vivante that more performance could be gotten from an optimized SDRAM controller.

Now if you’re not very familiar with SDRAM controllers, you might think there’s not much difference in controller designs. After all, they just take memory requests and feed them to the SDRAM. Right? Not so. SDRAMs actually have pretty complex access protocols these days and there are three ways to execute these protocols: efficiently, inefficiently, and wrong.

Exercise an SDRAM incorrectly—outside of the specified protocols—and you can lose data. (Note: That’s a bad thing.)

Exercise an SDRAM inefficiently by ignoring a few of the SDRAM’s access timing requirements, and you’ll lose a lot of the raw memory bandwidth you’ve paid for. (Note: That’s not so good either.)

So you want to be protocol-efficient to get your money’s worth from the SDRAM, but efficiency actually depends on the workload characteristics. Some accesses can overlap others. Some can not. So it makes sense to optimize the memory controller for the task.

From Vivante’s perspective, a good DDR memory controller

  • Allows multiple clients (GPU cores, CPU cores, DSP cores, and other logic) to share one SDRAM array
  • Delivers low latency for critical transactions
  • Delivers high bandwidth for large transfers
  • Reorders transactions to maximize SDRAM bandwidth (a gain of 30% is possible here)
  • Uses the SDRAM’s low-power modes and access methods where possible to reduce SDRAM power consumption

For these reasons, Vivante collaborated with Cadence to optimize the design of the configurable Cadence DDR memory controller core for Vivante’s graphics application. Specifically, the controller was customized to allow out-of-order reads and writes to hide SDRAM latency and to make efficient use of available memory bandwidth, to break memory objects up and distribute them to multiple banks, and to perform GPU-aware memory allocation. These modifications resulted in a 34% performance improvement for a read-oriented test, an 83% performance improvement for a write-oriented test, and a 22% performance improvement for an application-oriented test.

Note that it’s the joint collaboration between Vivante and Cadence that produced this significant improvement in overall performance. Optimizing the GPU and the memory-controller cores independently might never have achieved such a large improvement because interlocking improvements to both core designs work with the SDRAM’s innate characteristics to achieve the resulting performance boost.

Posted in DDR, DRAM, SDRAM | Tagged , , , , , | Leave a comment

Agilent: Memory technology has hit a wall due to physics limitations and that has implications for your designs

Last week, Agilent ran a seminar in Milpitas, California. The first of three subseminars was about memory technology with an excellent overview of the state of memory technology today. It was presented by Gordon Getty, an Agilent Application Engineer based in Santa Clara, California. Getty’s seminar segment on semiconductor memory started with this attention-getting statement:

“Memory technology has hit a wall due to physics limitations and that has implications for your designs.”

Because of this wall, which relates to speed and power, memory technology has been bifurcating to meet the opposing needs of PCs and servers on one side, mobile and portable devices on the other. PCs and especially servers need speed at almost any price. Power consumption is a secondary consideration. Mobile applications need fast memory with low power consumption. Consequently, the semiconductor memory industry has been and is evolving different interface standards to meet the divergent needs of these application markets.

Getty divided semiconductor memory into six major categories and tied each category to typical applications:

  • DDR – PCs and servers
  • GDDR – Graphics boards and embedded systems (in the future)
  • LPDDR – Mobile and embedded
  • QDR – Specialty memory (QDR Consortium)
  • NAND/NOR – Semiconductor Flash for code and data storage
  • e-MMC/SD – Managed Flash memory for mass storage

Getty then ticked off each category with some top-line DDR characteristics:


  • Currently at 2133 Mtransfers/sec, heading towards 2.3 Gtransfers/sec
  • VDD: 1.5, 1.35, 1.25V
  • 3D stacking


  • 2.4Gtransfers/sec heading toward 3.2Gtransfers.sec
  • Big physics challenges forcing a transition like PCI to PCIe
  • Memory still resides in a parallel world, so DDR4 isn’t going serial, it going point-to-point


  • 6Gbps per pin heading to 8Gbps per pin in 2012
  • Point-to-point connections


  • LPDDR2: 800Mbps per pin heading to 1067Mbps per pin
  • LPDDR3: 1600Mbps

The increase in the rate of speed for per-pin memory connections is leveling off due to the physics of the situation, said Getty as he showed a slide with the signature curves showing a technology reaching maturity.

“Memory is finally boxed in by physics,” he said. Memory interface designers must make compromises in per-pin transfer rates and the number of parallel data pins in the interface. As physics enforces its laws, the number of data pins tends to go up but there are limits there too. More pins means more manufacturing issues and reliability starts to drop.

Does that mean we’ve hit a brick wall? Perhaps not, said Getty. It’s possible for memory to take the serial route the way the parallel PCI interface has evolved into the PCIe serial interface spec, which initially supported 2.5Gtransfer/sec per pin and now has been extended to 8Gtransfers/sec per pin. With new coding, PCIe at 8Gtransfers/sec per pin delivers four times the data rate of the 2.5Gtransfer/sec rate.

Getty then said that the key system-level memory design challenges are:

  • Increasing system failures due to more pins and higher speeds
  • Standards compliance (need to build this in from the start)
  • Signal integrity (increasingly critical as transfer rates rise)
  • Timing margin
  • Probability (for physical testing of manufactured systems)

Agilent presented this seminar because it offers measurement and analysis tools for a variety of memory interface standards.

Note: Cadence offers design IP, memory models, and verification IP for a variety of memory devices.

Posted in 3D, DDR3, DDR4, DRAM, eMMC, Flash, LPDDR2, LPDDR3, NAND, NOR, QDR, SD, SDRAM, Storage | Tagged , , , , , , , , , , , , | 1 Comment

DRAMeXchange opines on six major DRAM and NAND Flash trends for 2012-2015. What do you think?

The DRAMeXchange http://www.dramexchange.com/ keeps a very close watch on the spot and contract prices for all forms of semiconductor memory including DRAM and NAND Flash devices. The group also keeps an eye on trends that may affect pricing. A couple of days ago, the DRAMeXchange pronounced six major trends expected to affect the DRAM and NAND Flash markets for the next three years. In order, these trends are:

  1. DDR3 SDRAM will dominate the PC market until 2014.
  2. LPDDR3 SDRAM will supplant LPDDR2 SDRAM in mobile application by 2013 while the fate of Wide I/O SDRAM hangs on the successful maturation of 3D IC assembly.
  3. The Ultrabook market is a tossup between DDR3L and LPDDR3 SDRAM.
  4. If SSD unit costs drop below $1/Gbyte, they will see explosive growth as Ultrabooks adopt SSDs over hybrid HDD/SSD designs.
  5. SATA 3.0 HDDs will become the mainstream interface for PC SSDs in 2012 but the advent of ONFI 3.0 and Toggle DDR2.0 NAND Flash devices will mean that SSD vendors will be forced to adopt even faster interfaces such as PCIe in two to three years.
  6. NAND Flash usage in Ultrabook and smartphone designs will increase to the detriment of SDRAM capacity because of relative price/performance metrics.

See the full description of the DRAMeXchange predictions here.

Also, consider signing up for Memcon in September. Click on the MEMcon logo over there on the right-hand side of this page.

Posted in 3D, DDR3, DDR4, DRAM, Flash, HDD, LPDDR2, LPDDR3, Memcon, ONFI, Toggle | Tagged , , , , , | Leave a comment

More on developing your own SSD controller chip. Is rolling your own right for you?

A couple of days ago, I described the new STEC MACH16 SSD and noted that STEC had developed its own SSD controller and firmware. (See “STEC’s MACH16 Slim 2.5-in SATA SSD requires small footprint, fits in small embedded spaces”) I did the same for yesterday’s introduction of the yet-to-be-named Micron 2.5-inch, PCIe SSD, which also employs a proprietary controller. (See “Micron introduces Enterprise-class, 2.5-inch SSD with PCIe interface”). So now seems like a good time to introduce you to an article that appeared last month on the SSD Review Web site (“Examining The SSD Industry – Researching The Controller or Processor”) In this article, author Wayne Eisenberg, retired Vice President of Worldwide Sales and Marketing Communications at SMART Modular Technology, notes that several vendors that have developed their own SSD controllers and firmware. Eisenberg writes:

“If the controller is the engine, than the firmware is the steering, transmission, accelerator and braking system, all in one. The engine (controller) can’t run without the fuel (NAND), however is arguably useless without direction and control, the firmware.”

You might want to give the article a closer look. There might be some competitive advantage in there for you.

Naturally, if you need some appropriate design IP, verification IP, or memory models to develop your own SSD controller SoC and firmware, Cadence might be able to help. Give us a call.

Posted in Flash, NAND, SSD | Tagged , , , | 3 Comments

Micron introduces Enterprise-class, 2.5-inch SSD with PCIe interface

This week, Micron announced a hot-swappable, 2.5-inch SSD that employs a PCIe interface instead of the more widely used SATA or SAS disk interfaces. Dell announced that it has selected this drive for its 12th generation PowerEdge server line. Both Micron and Dell are members of the SSD Form Factor Working Group (www.ssdformfactor.com) , which is working to further the adoption of PCIe storage drives.

Micron adapted its RealSSD P320h PCIe board-based SSD (introduced last year) for the electrical design of the new SSD, which look’s like a conventional, aluminum-encased 2.5-inch drive. The P320h design uses a proprietary Micron SSD controller chip that can operate 32 channels of NAND Flash memory and sports a PCIe Gen 2 x8 interface. The new 2.5-inch SSD uses a PCIe Gen 2 x4 interface and is available in capacities of 175Gbytes or 350Gbytes—the board-based P320h SSD is available with a capacity of 350Gbytes or 700Gbytes.

Micron is currently sampling the new 2.5-inch SSD.

Pssst: Need some verification IP for PCIe Gen 1, 2, or 3? Check this out.

Posted in NAND, SLC, SSD, Storage | Tagged , , , , , , | 5 Comments

Is Flash memory nearing end of life and if so what solid-state storage is waiting in the wings? Will that be the salmon or the rosemary chicken?

On Thursday, May 17, the inaugural Storage Valley Supper Club sits down for its first dinner in Milpitas, California to discuss the state of the storage industry (“Because it’s all about storage!”). Anyone with present or past affiliations in the storage arena including components, drives, systems, and software is welcome to attend. Oh, you’ll need $40.97 to pay for the dinner too. (Will that be salmon, the rosemary chicken, or eggplant parmesan?)

The main topic on the agenda is a panel discussion titled “Storage Roadmaps: The Hitchhikers Guide.” Presenters include:

  • Steve Hetzler, an IBM Fellow at IBM’s Almaden Research Center in San Jose, California where he manages the IBM Storage Architecture Research group. He’s got 35 storage-related patents under his belt too.
  • Jim Handy, a leading analyst in the industry who has focused on semiconductor memory and storage for the last two decades
  • Tom Coughlin, author of “Digital Storage in Consumer Electronics: The Essential Guide” and the man behind the annual Storage Visions and Creative Storage conferences

The discussion topics include:

  • Is flash memory nearing end of life and if so what solid state storage is waiting in the wings?
  • When will HDDs achieve higher areal density growth and what technologies will drive it?
  • What is the future role of optical discs and magnetic tape in the storage hierarchy of tomorrow?
  • What are current and future applications for cloud storage?
  • What are future roles of various storage devices in system architectures?
  • What is the current situation with the storage supply chain—are we one earthquake or flood away from a major disaster?

Forget the salmon, the chicken, the eggplant, the salad, the baby carrots, and the unlimited soda—where else will you get this kind of information about the storage market for 40 bucks?

The venue is “Dave and Busters” at the Great Mall in Milpitas, CA.

Who says these guys don’t have a sense of humor?

The date again is Thursday, May 17.

Register here before all the seats are gone. Tell ‘em “Steve sent you.”

Posted in NAND, SSD, Storage | Tagged , , , , | Leave a comment

Free Webinar on using NOR Flash memory—sponsored by Avnet and Spansion. March 13

Avnet and Spansion are sponsoring a free Webinar on using Spansion’s GL-S NOR Flash memory, which is available in capacities of 128Mbytes to 2Gbytes. Although NAND Flash memory gets most of the attention these days, NOR Flash memory is apparently alive and well—suitable for a range of applications including “automotive in-cabin electronics, consumer electronics, gaming, industrial, set-top box, telecommunications and networking.”

The Webinar takes place on March 13 and starts at 9:00 am PST. Register here.

Posted in Flash, NOR | Tagged , , , , | Leave a comment

STEC’s MACH16 Slim 2.5-in SATA SSD requires small footprint, fits in small embedded spaces

STEC has introduced a small-form-factor Slim SATA SSD with a Slim SATA interface for embedded and other computing applications that require lots of storage that can fit in a small space and consume little power. The STEC MACH16 SSD is available in capacities of 25 to 50Gbytes. The SSD measures approximately 54x40x4mm, so it can be tucked into small, available volumes within an end product and connected to a motherboard using conventional 22-pin SATA cabling. Power consumption is said to be “typically under 2W.” (A bar graph of the power consumption suggests 1W.)

Significantly, STEC’s MACH16 Slim SATA data sheet says that the drive uses a proprietary SSD controller originally developed for the company’s MACH8 SSD. The data sheet also directly addresses reliability concerns by saying that the Slim SATA Mach16 SSD uses “a combination of write and erase management techniques; read-level adjustments; write-softening techniques; digital signal processing methods for signal/bit detection; and other management technologies to increase NAND cell life and endurance, as well as performance,” which the company rolls into one term: CellCare. STEC has published a White Paper with an overview of its CellCare technology, which you can find here.

Because of this focus on data integrity, STEC is positioning this SSD as an “enterprise-class drive for the embedded market.” STEC’s focus on the controller and algorithms used in the MACH16 Slim SATA SSD again telegraph where the future battle for SSD leadership is headed. As NAND Flash devices continue to ride the Moore’s Law process technology curve into the 20nm-and-below region, raw NAND Flash memory cell endurance becomes more of an issue that must be dealt with through an array of algorithms that manage the error and wearout failure mechanisms inherent in raw NAND Flash technology. As a result, STEC obviously chose to develop a proprietary controller and firmware to differentiate its SSDs in the marketplace.

More information on the STEC MACH16 SSD is available here.

Posted in Flash, NAND, SSD | Tagged , , , , , , , , , , | 4 Comments

Get the specifics of designing DDR3 SDRAM into a pcb with timing closure and good signal integrity

Next week at CDNLive!, EMA Design Automation will give a presentation on designing DDR3 SDRAM into a pcb with attention given to the signal integrity issues and timing closure. This session is one of seven pcb-specific sessions at CDNLive! on Wednesday, March 14. For more information on these sessions, click here.

Posted in DDR3, SDRAM | Tagged , , , | Leave a comment

MRAM pairs with digital neuron chip to create pattern-recognizer board stackable to 1M neurons

Last week at the Embedded World 2012 event in Nuremberg, Germany, CogniMem Technologies demonstrated its 4096-neuron CogniBlox module that combines four of the companys 1K-neuron CM1K chips with 4Mbytes of Everspin MRAM. The MRAM is used to quickly load stored neuron patterns and to quickly save patterns for shifting among multiple recognition tasks on a real-time basis. CogniMem selected MRAM because of its fast read/write speed combined with its nonvolatility. A Lattice FPGA ties together the four CM1K neuron chips with the two MRAMs and the boards are stackable so that you can build a 1M-neuron system with 250 stacked boards. Such a system would deliver 0.13 petaflops with a power consumption of 500W.

For more information on the CogniBlox module, click here.

You’ll find Everspin MRAM memory models and 6000 more SOMA memory models for RAM and Flash devices at www.eMemory.com.

Posted in MRAM | Tagged , , , | Leave a comment

More DDR4, DDR3, and 3D IC technical details from ISSCC, courtesy of memory analyst and expert Jim Handy

Semiconductor memory analyst and expert Jim Handy has just published an overview of some memory papers given at last week’s ISSCC. Handy’s article on the ElectroIQ web site supplements some of the previous Denali Memory Report blog entries published earlier this week. Among Handy’s tidbits:

  • Samsung’s paper highlighted the clock circuitry in the company’s 39nm implementation of a a 4Gbit DDR4 SDRAM. The memory chip performs parity generation and checking on the address and command lines and uses CRC generation and checking on the data.
  • Hynix described a 38nm implementation of a 2Gbit DDR4 SDRAM that runs at 1.2V. The chip has a die size of 43.15mm2 and power consumption is said to be about 50% less than the equivalent DDR3 SDRAM even though the DDR4 and DDR3 memory cores operate at the same frequency. That says a lot about the on-chip peripheral circuitry and the I/O schemes.
  • Hynix also described a DDR3 SDRAM built with 23nm process technology resulting in a die size of 30.9mm2.
  • Hynix described a special clocking scheme for TSVs (through-silicon vias) that aligns the clocks for all SDRAMs in a multi-die 3D stack.

You’ll find Handy’s full article here.

For earlier Denali Memory Report blog posts connected to last week’s ISSCC, see:

SanDisk shows 128Gbit, 3-level cell NAND Flash memory chip at ISSCC. Is 20nm (or 19nm) here, so soon?

SanDisk’s founder and retired CEO Eli Harari says that the future of SSDs, computer memory, and everything else belongs to memristors at 11nm

Operational DDR4 SDRAM prototypes appear at ISSCC

For more information on the Cadence DDR4 and DDR3 SDRAM controller IP, click here.

For more information on the Cadence DDR4 and DDR3 PHYs, click here.

Posted in 3D, DDR3, DDR4, DRAM, SDRAM | Tagged , , , , , , , , , | Leave a comment

Objective Analysis White Paper covers the basics of SSD design. Do you know what’s important?

Jim Handy at Objective Analysis has just published a White Paper about SSDs titled “Enterprise Reality, Solid State Speed.” The White Paper provides an excellent introduction to issues surrounding SSD design. The key issue here is the basic wearout failure mechanism inherent in NAND Flash memory. Handy writes:

“NAND Flash is a messy medium. One means by which chip architects pushed NAND Flash costs below those of NOR Flash (or any other memory technology for that matter) was by compromising data integrity.”

But don’t let that scare you. Handy continues:

“In a move borrowed from the HDD industry, NAND Flash stores data in a way that anticipates data corruption, then requires an external controller to scrub the data every time it is read fro the device.”

Sound messy? It is, but no messier than the issues HDD designers have had to deal with for many years. This same sort of problem has been the driver behind the development of increasingly powerful error checking and correction (ECC) specifically developed for the unique failure mechanisms of the HDD.  As Handy writes:

“Fortunately, error correction coding (ECC) is well understood, and ECC is keeping pace with the degradation of NAND data integrity, offsetting increases in Flash error rates.”

If you think that this sort of thing cannot go on forever, you’re right. Handy continues:

“However, another difficulty adds to this trouble. NAND Flash has a wear-out mechanism that is unique to this technology. After a large number of erase/write cycles, bits start to lock up and can no longer be used. This adds to the number of bits that the ECC must correct. As an increasing number of bits become unusable, errors rise to approach the limits of the ECC engine’s capabilities. At this point, that particular block must be removed from the pool of available memory.”

Total block failure then leads to the next level of error protection that must be built into the SSD: reserve blocks, also known as overprovisioning.

ECC must occur quickly and is usually implemented in the hardware of the NAND Flash controller. Because the required amount of ECC changes with each generation of NAND Flash device, you generally want to look for a controller with a flexible ECC capability.

Overprovisioning is a strategy that varies by SSD design, so it’s most often handled in the firmware that drives the NAND Flash controller. A very recent example of this is the release by LSI Corp late last month of new firmware for SandForce SSD controllers that boosted drive capacity roughly 7% without changing the required amount of raw NAND Flash memory. (See “LSI Releases Code To Manufacturers – New Increased Capacity ‘SandForce Driven’ SSDs Hit The Streets”.) The added capacity came from a new overprovisioning strategy implemented in the firmware for the SandForce SF-2000 series of SSD controller chips. So, when picking a controller, you also want to know that the controller vendor is on the ball with up-to-date firmware that is frequently updated to extract the most performance and capacity from the current generation of NAND Flash memory. You also want to be sure that you understand the performance, reliability, and endurance goals that drove the development of that firmware.

For a copy of the Objective Analysis SSD White Paper, click here.

For information on the Cadence NAND Flash memory controller, click here.

Posted in Flash, SSD | Tagged , , , , , , , | Leave a comment

SanDisk shows 128Gbit, 3-level cell NAND Flash memory chip at ISSCC. Is 20nm (or 19nm) here, so soon?

I’ve already written about retired SanDisk CEO Eli Harari’s ISSCC keynote prediction that ReRAM/memristor technology would supplant DRAM and NAND Flash memory by the time the 11nm process node arrives. (See “SanDisk’s founder and retired CEO Eli Harari says that the future of SSDs, computer memory, and everything else belongs to memristors at 11nm”) Well, there was another major revelation in Harari’s keynote speech. He showed SanDisk’s latest production NAND Flash device—developed jointly with Toshiba—a 128Gbit Flash memory that employs 3LC/TLC (three-level cell) storage. According to a post on www.techspot.com (“SanDisk 19nm 128Gb flash memory chip is world’s smallest”), SanDisk is using 19nm process technology.

If Harari’s prediction about ReRAM/memristors is correct NAND Flash’s dominance as the process driver of choice has one or two more process generations left. Previous process drivers have included DRAM, microprocessors, and FPGAs.

Posted in Flash, Memristor, NAND, ReRAM | Tagged , , , , , , | 1 Comment

SanDisk’s founder and retired CEO Eli Harari says that the future of SSDs, computer memory, and everything else belongs to memristors at 11nm

The SSD Review reports that SanDisk’s founder and retired CEO Eli Harari delivered some explosive predictions at last week’s ISSCC in San Francisco. In sharp contrast to the recent and highly publicized paper predicting the slowdown of SSD speed and reliability that surfaced a couple of weeks ago (see “The sky is falling! The sky is falling! Paper predicts the bleak future of SSDs and NAND Flash memory”), Harari says that SSDs will “checkmate” hard drives by the year 2020. That’s eight years from now. The bigger bomb, perhaps, is Harari’s assertion that  resistive RAM (3D ReRAM, also called memristor RAM by some) will become the preferred medium for storage devices. Should that be the case, then ReRAM/memristor technology will also overcome DRAM, which as Harari pointed out in his keynote is already at a 10x cost/bit disadvantage compared to NAND Flash memory. “And that’s not likely to change,” said Harari.

Click here for the article in the SSD Review.


Posted in 3D, Flash, HDD, Memristor, ReRAM, SDRAM, SSD | Tagged , , , , , , | 2 Comments

Operational DDR4 SDRAM prototypes appear at ISSCC

As reported this week by several Web sites including Techeye.net, Samsung and Hynix both demonstrated working prototypes of DDR4 SDRAM at the ISSCC conference in San Francisco this week. The Samsung and Hynix DDR4 memories were manufactured in 30nm and 38nm process technologies respectively but production chips will use smaller lithographies when the memories go into volume production later this year. According to the Techeye article you can expect to see Micron, Elpida, and Nanya enter the DDR4 fray later this year as well.

For more technical information about DDR4 memories, see “The DDR4 SDRAM spec and SoC design. What do we know now?

For information on the Cadence DDR4 SDRAM controller IP block, just in case you’re working on an SoC in the server space that might need one, click here.

Posted in DDR4, SDRAM | Tagged , , , , , , , , , | 1 Comment

SMART Storage Systems’ Optimus Ultra SSD taps consumer-grade NAND Flash memory with magic wand named Guardian to make enterprise-class SSD

A lead from Computerworld put me onto the announcement by SMART Storage Systems of a new enterprise-class Optimus Ultra SSD based on consumer-grade MLC (multi-level cell) NAND Flash devices. Using consumer-grade silicon to make this drive cuts the OEM cost per Gbyte by about half, so there’s real incentive to come up with something very clever to enable this design approach.

Enterprise-class storage requires more data reliability under harder use than consumer-grade NAND Flash is designed to accommodate, so making a high-grade SSD from lesser-grade NAND Flash is an interesting exercise in system development. As the Computerworld article says, consumer-grade MLC NAND Flash chips are rated for perhaps 3000 program/erase cycles and that sort of raw endurance would be fatal for an enterprise-class SSD. The new Optimus Ultra SSD from SMART Storage  has an endurance rating of 100,000 program/erase cycles, so something pretty interesting is going on inside of the box.

The Computerworld article say this about the way SMART Storage boosts drive endurance:

“SMART Storage achieves its NAND flash endurance through a combination of aggregated flash management and signal processing techniques. Aggregated flash management combines writes to reduce wear and signal processing increases the signal-to-noise ratio, making it possible to continue reading data even as electrical interference rises as electrons leak between flash cells.”

Uh huh.

Write combining to reduce the number of write-erase cycles is a well-known technique. Any good SSD controller should be able to support that, although there are clever ways to do it and then there are ways that are even more clever. However, what’s this stuff about signal processing? How do you get at the information needed to evaluate cells inside of a NAND Flash device?

I checked with the SMART Storage Web site to seek more illumination and found this video on the Company’s so-called Guardian Technology:

And then I found this article on the StorageReview.com site. The article explains that SMART Storage System’s Guardian Technology consists of three component technologies. The first, called FlashGuard, intelligently manages the Flash media. It maximizes the use of “stronger” Flash cells and minimizes the use of weaker cells. A key characteristic of Flash memory devices is that some cells do have less endurance and those weaker cells set the endurance spec for the entire Flash chip if all of the on-chip cells are treated equally. SMART Storage has figured out how to detect, map, and isolate these weaker cells at manufacturing time to increase system endurance. FlashGuard also employs a proprietary ECC algorithm to further boost data integrity.

The second endurance-boosting component technology in the Guardian triad is called DataGuard, which combines data-path protection, ANSI T10 DIF (data integrity field) protection blocks (just like the big boys use), and cross-die redundancy.

The third component technology is called EverGuard, which appears to be an internal power-backup technology based on capacitive energy storage, coupled with some architectural features that manage internal drive power more effectively to ensure that scheduled writes can occur even when system power is lost.

Together, these technologies telegraph a truth in the SSD market. It’s not going to be possible to just slap an SSD together using standard NAND Flash memories, an off-the-shelf controller chip, and some vendor’s standard SSD firmware and hope to compete for high-margin opportunities. SMART Storage has obviously put a lot of thought into the design of the Optimus Ultra SSD to make it stand out in a market that becomes more crowded by the day.

How will your SSD development team do the same?

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Is Wide I/O SDRAM a disruptive technology? Signs say yes according to new EETimes article

A new article about Wide I/O and 3D IC assembly published in EETimes brings some additional technical information to light. The article was written by Marc Greenberg and Samta Bansal, both from Cadence, and it contains both a review of successful 3D IC assembly projects to date and an overview of the advantages Wide I/O SDRAM provides to system-level designers. The successful 3D IC projects noted include the Xilinx Virtex-7 2000T FPGA—which uses a silicon interposer to consolidate four FPGA tiles into one large FPGA—and the WIOMING 3D project jointly developed by ST-Ericsson, CEA-Leti, ST Microelectronics, and Cadence Design.

I’ve called Wide I/O SDRAM, based on the JEDEC JESD229 spec, the killer app for 3D IC assembly several times and this article provides more concise technical reasons why this is so. The article states:

“With its 512-bit data interface, JESD229 Wide I/O Single Data ¬Rate (SDR) doubles the bandwidth of the Low-Power Double Data Rate 2 (LPDDR2) specification without increasing power consumption.”

It then provides this graphic, which sort of says it all:

Low-Power DRAM Memory Bandwidth per Package, by Intro Date

As you can see from this graphic, Wide I/O SDRAM is a disruptive technology that really jumps performance while maintaining current power-consumption levels. This is the sort of technology that’s catnip to system designers.

Where will we see Wide I/O memory used first? Here’s what the article has to say:

“Like many new technologies, TSV has an initial cost that is higher than the technology it replaces, and simply reducing the cost of the dice in the stack may not be enough to justify its use. The ideal applications for TSV technology are those that can benefit from the dramatic improvement it brings to bandwidth, latency and power.”


For more information on the WIOMING project, see:

3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say ‘Tour de Force’?

3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

For more information on Wide I/O SDRAM and the JEDEC JESD229 spec, see:

3D Week: JEDEC Wide I/O Memory spec cleared for use

3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?

3D Thursday: Boosting the bandwidth of Wide I/O SDRAM to 1 Tbit/sec through standards evolution

3D Thursday: Is Wide I/O SDRAM free for the end user???

For more information on the Xilinx Virtex-7 2000T FPGA, see:

3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!

Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)

3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)

3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology

3D Thursday: Is 2.5D IC assembly ‘buzz-worthy’?

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The sky is falling! The sky is falling! Paper predicts the bleak future of SSDs and NAND Flash memory

An interesting and disturbing paper titled “The Bleak Future of NAND Flash Memory” written by two researchers at the Department of Computer Science and Engineering at the University of California, San Diego, and one Microsoft employee uses current trends with NAND Flash memories and SSD (Solid-State Disk) designs to cast the future of these technologies in a rather dim light. First, the bad news: there’s a definite endpoint where the diminishing returns from existing NAND Flash technology become so small that SSD design based on NAND Flash memories essentially halts at a predicted SSD capacity of 4.6Tbytes for MLC (two-level cell) NAND Flash memories and 14Tbytes for TLC (three-level cell) NAND Flash memories. It takes a lot of empirical measurement, math, and graphing in the paper to derive that number and if you want to see it in all the gory detail, then read the paper. Meanwhile, I’ll summarize the arguments here if you want the short(er) version.

NAND Flash memory makers optimize for volume and the volume driver for NAND Flash at the moment is USB memory drives. These USB drives completely replaced floppy disks about a decade ago and, consequently, NAND Flash memory chips have some very specific characteristics peculiar to removable media.

8-inch, 5.25-inch, and 3.5-inch Floppy Disk Drives

The important figures of merit for Flash-based USB drives are capacity and price/bit. Further, these solid-state USB drives are not written often. They serve as backup and data-transfer devices. Because of these figures of merit, NAND Flash vendors have been pushing capacity and cost/bit at the expense of other parameters. NAND Flash vendors ride the scaling curve of Moore’s Law as hard as they can, with 25nm and “20nm-class” commercial devices now in production. NAND Flash manufacturing is way ahead of production DRAM and logic lithographies. At the same time, NAND Flash vendors have started to pack two or more bits into each logic cell using the inherent analog nature of the NAND Flash charge-storage mechanism to correlate the amount of stored charge with a mutlibit value.

As a result of these optimizations, several important characteristics of NAND Flash memories degrade as bit density and cost/bit improve. In particular, performance (read/write speed) and reliability suffer. Taking these trends to an extrapolated conclusion, the authors write “…it will be extremely difficult to design SSDs that reduce cost per bit without becoming too slow or too unreliable (or both) as to be unusable in enterprise settings. We conclude that the cost per bit for enterprise-class SSDs targeting general-purpose applications will stagnate.”

Grim news indeed.

Or is it? After all, it’s only a prediction, so far.

Popular online summaries of this paper dwell on the inevitable winding down of SSDs in the future—perhaps over the next ten or twelve years. But before we start to run around like Chicken Little and proclaim that the sky is falling, let’s take a look at the assumptions the authors have made because they exert a significant bias to the conclusions. Perhaps things are not as bleak as the paper’s title might have us believe.

One of the key elements used to create the paper’s dire forecast is the creation of a formal model of an SSD called the “SSD-CDC” or “SSD with a constant die count.” Here’s the reasoning: Current commercial SSD controller chip architectures implement 24 NAND Flash control channels with each channel handling a maximum of four NAND Flash die. So the SSD-CDC can accommodate no more than 96 NAND Flash memory die. The “SSD-CDC’s architecture is representative of high-end SSDs from companies such as FusionIO, OCZ and Virident,” write the authors.

The 96-die limitation is an important limiting assumption in this paper. Given a physical limitation with respect to die count per SSD, the only way to increase drive capacity is to increase die capacity. You can ride Moore’s Law just so far and in this paper the authors ride Moore’s Law all the way to 6.5nm process geometries from a 34nm baseline.

Another capacity dimension is the number of bits stored in each  NAND Flash memory cell. The authors ride the bit/cell dimension to three (three-layer cell (TLC) NAND Flash die). With the number of die limited to 96 and the number of bits/cell limited to three, the authors hit a 14Tbyte ceiling for SSD capacity when the geometries hit 6.5nm.

Well, 14Tbytes isn’t a bad capacity, at least not today, but it’s the latency and bandwidth limitations that worry the authors more. They write, “Reaching beyond 4.6 TB pushes write latency to 1 ms for MLC-2 and over 2.1 ms for TLC. Read latency, rises to least 70 μs for MLC-2 and 100 μs for TLC… Either SSD-CDC’s capacity stops scaling at ~4.6 TB or its read and write latency increases sharply because increasing drive capacity with fixed die area would necessitate switching cell technology from SLC-1 or MLC-1 to MLC-2 or TLC-3… SSDs offer moderate gains in bandwidth relative to disks, but very large improvements in random IOP performance. However, increases in operation latency will drive down IOPs and bandwidth.”

Do you believe this? Is it true?

Given the authors’ assumptions, it might well be true, if all factors stay constant.

However, all factors are not constant no matter what kind of technology you’re talking about.

Perhaps the biggest factors to discuss here—although not the only ones—are 3D IC assembly and 3D IC manufacturing. First, the NAND Flash vendors know they are in a situation of diminishing returns and have started to seriously consider 3D IC manufacturing to allow a Z dimension in the construction of individual NAND Flash memory cells. (See “3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron” and “The End of NAND Flash as we Know It: Micron’s Dean Klein and Samsung’s Tony Kim Look at Life After Flash”)

Micron 3D NAND Flash Memory Cell

Multi-level and triple-level NAND Flash cells are not the only way to skin the cat, so to speak, and 3D IC manufacturing could revolutionize NAND Flash manufacture as early as next year. Micron, Samsung, and Toshiba have all discussed 3D NAND Flash cell architectures at public events. The onset of 3D NAND Flash memory cells will certainly affect some of the latency and bandwidth assumptions in the “Bleak Future” paper.

Next, consider 3D IC assembly. The notion of limiting each NAND Flash controller channel to four die is based, in part, on a pcb real-estate calculation that doesn’t take 3D IC assembly into account. You can save a lot of real estate using 3D IC assembly techniques so the assumed 4-die/channel limitation might therefore fall by the wayside.

You could also call into question the 24-channel limitation itself. Again, more reliance on 3D IC assembly techniques might well throw the channel limitation into limbo as well. There’s nothing inherently “right” about 24 channels. It’s not even a power of two.

Finally, NAND Flash might not be the technology of the future at all for SSD storage. There are other technologies at various stages of production readiness set to challenge NAND Flash semiconductor storage. MRAM (magnetic RAM) is in early-stage production at Everspin and a handful of players including Everspin seem poised to introduce STT (spin-torque transfer) MRAM, which could well prove to be a real challenger to NAND Flash memory. (See “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit”) In addition, there’s lots of news lately about memristor and memristor-like memory, although nothing’s yet reached production. (See “HP’s memristor finds a commercial semiconductor vendor: Hynix”.) The characteristics of these new memory technologies will also alter the landscape with respect to the assumptions discussed above. There’s no law that says SSDs must be built with NAND Flash memory.

So, in short, the “Bleak Future” paper is effective in pointing out some imminent pitfalls but we don’t know how long SSDs will really last because technological disruptions prevent the smooth evolution of storage devices and stymie this sort of analysis.

Let me leave you with three lessons from memory and storage history:

  1. Magnetic core memory reigned as the random-access memory of choice for 20 years—from about 1953 when the MIT Whirlwind computer became the first electronic computer to use magnetic cores through the early 1970s. Within two years of the Intel 1103 DRAM introduction in 1970, magnetic core memory production dropped off the cliff. That’s how fast a memory revolution can take place if the new replacement technology is sufficiently compelling. (Note: magnetic memory may make a comeback if commercial MRAM succeeds.)
  2. The first commercially available 8-in floppy disk drive—from IBM—appeared in 1971. For decades, floppy disks regularly grew in capacity and shrank in physical volume—only to be far outpaced by size of media files, the growth in software program footprint, and the capacity increases enjoyed by hard disk drives. After three decades, the gap between floppy capacity and the immediate needs for removable storage caused the mighty floppy disk drive to fall by the wayside and solid-state USB drives got their chance to shine as NAND Flash memory technology finally came into its own—after 15 years of development.
  3. The demise of hard disk drives has long been predicted. Analysts said that the rate of capacity increase for a hard disk drive was unsustainable. They were wrong. Often. Consistently. The magneticians continued to find and exploit amazing new magnetic properties so that 3.5-inch hard drives now have Tbyte capacities. Some of these amazing developments included giant magnetoresistance and PRML (Partial Response Maximum Likelihood) coding.

The lesson from these three examples is that technological revolutions are impossible to predict accurately, as are their effects.

Want to hear more about these topics? Well, Memcon 2012 is coming in September and the registration page is now open. Click here.

Posted in 3D, Flash, Memcon, Memristor, Micron, MLC, MRAM, NAND, SSD | Tagged , , , , , , , , , , , | 3 Comments

STT MRAM startup Spin Transfer Technologies secures $36M in Series A funding

Last week, STT MRAM startup Spin Transfer Technologies announced that it had secured $36M in Series A financing from Allied Minds and Invesco Asset Management. Spin Transfer Technologies is developing an “orthogonal” version of STT (spin transfer technology—the technology, not the company) MRAM (magnetic RAM) cells, which the company STT claims “far exceeded industry standards in key [performance] areas.” Spin Transfer Technologies—the company—was established by Allied Minds and New York University to develop and commercialize orthogonal spin transfer magnetoresistive random access memory technology, OST-MRAM.

MRAM is one of the serious challengers to the status quo in semiconductor memory. If made commercially viable in terms of speed and density, MRAM could challenge both DRAM and NAND Flash semiconductor memory.

For more information on MRAM and STT MRAM see “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit” and “Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC NV memory?

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Flash Memory Summit 2012: Call for presentations

Planning is now underway for the Flash Memory Summit 2012, which will be held in Santa Clara, CA in August. There’s no better show devoted exclusively to NAND Flash semiconductor memory and applications of NAND Flash—particularly SSDs. The organizers have put out a call for presentations, so click here for more info and be sure to save space on your calendar for the event, August 21-23.

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Is Wide I/O SDRAM free for the end user? (Republished from EDA360 Insider)

Note: I just published this blog entry on my EDA360 Insider blog for 3D Thursday but the topic is so relevant to the conversation in the Denali Memory Report that I am republishing it here as well.

Samsung Wide I/O SDRAM die (Definitely NOT free)

A recent email from Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, suggested that Wide I/O used in a 3D stack is free for the end user. In other words, there’s no incremental cost in the purchase price of an end product (such as a mobile phone or a tablet) that pairs Wide I/O SDRAM with a logic chip using 3D assembly techniques. Greenberg challenged me to check his math. I’m going to do just that in this blog post. See what you think.

We need to start with the incremental cost of adding TSVs (through silicon vias) to a multiprocessor SoC (MPSOC). To do that, we need to figure out much added cost there would be to add TSVs to an MPSoC die.

Well, how big is an SoC or MPSoC die that might use a Wide I/O SDRAM?

Without naming names, let’s look at a series of such SoCs from one vendor. This SoC family includes single- and multi-processor designs built with 65nm and 45nm process technology. Die sizes range from 40 to 110 mm2. Marc then conjectures that a “representative” applications processor SoC measures 9x9mm, giving an area of 81mm2. That’s right in the middle of the range for the existing application processor family described above.

You can fit approximately 800 such die on a 300mm wafer. (Marc provided a handy reference pointer for this computation.) Let’s suppose we get about 70% yield from this wafer (or pick your own yield number), resulting in 560 known good die per 300mm wafer.

Now all we need to do is figure out the incremental cost per wafer for adding the TSVs. Here, the numbers are all over the map. At the recent 3D Architectures for Semiconductor Integration and Packaging event held in Burlingame, California, I heard incremental cost numbers as high as $800 per wafer for adding TSVs. I’ve also read estimates of $150 (click here) and seen an estimate that the ultimate cost will be about $25 (click here) once we get the process nailed down.

What number should we use?

Let’s pick something between $150 and $800 that doesn’t require too much “hard” math. How about $560? That would make the incremental cost of adding TSVs to an SoC work out to exactly $1 per known good die. You can’t get much easier than that. If you prefer the $150 number, then it’s 27 cents per die. If you believe that eventually it will cost $25 per wafer to add TSVs, then the incremental cost is 4.5 cents per die.

In the end, you’ll see it doesn’t really matter which of those three per-die incremental costs you pick. You win in any case.

Why? Because, as Marc has been known to say, the power savings you get from using Wide I/O SDRAM permit you to shrink the battery powering the end product. You can save $1 to $3 in the battery alone from those power savings, not to mention the board-cost savings derived from reducing the IC real estate footprint when the SDRAM disappears from the board and climbs on top of the application processor.

Now, before you get all technical on me, let me acknowledge that there are a host of factors not included in this SWAG cost analysis. Neither Marc nor I compared the relative cost of compression bonding the Wide I/O SDRAM to the SoC versus wire bonding. We did not include the cost savings of entirely eliminating the packaging for the Wide I/O SDRAM nor the incremental cost of the more complex encapsulation for the 3D stack. Also, we did not factor in the cost savings resulting from the elimination of some 120 fewer pins on the SoC, which no longer needs an external SDRAM interface, and we also did not factor in the yield loss due to stack assembly.

So, is this a back-of-the-envelope calculation? You betcha! Is it a good engineering estimate for making a decision to look more seriously into 3D integration. I’d say so.

By the way, Cadence offers a Wide I/O SDRAM controller and PHY IP plus an appropriate memory model for your SoC verification efforts, just in case you feel the sudden need to design an SoC with TSVs to pair with a Wide I/O SDRAM. Feel free to check them out.

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SanDisk launches X100 SSD in 2.5-inch, mSATA, and custom form factors. Capacities to 512Gbytes.

SanDisk has just jumped into full-fledged OEM mode with the X100 SSD series that is available in 2.5-inch (7 or 9.5mm thick), mSATA, and custom form factors and capacities of 32 to 512Gbytes. All drives are based on MLC (multi-level cell) NAND Flash memory and employ a 6Gbps SATA interface port. Sequential read/write speed is said to be “up to” 500/420 Mbytes/sec. Typical active power is rated at 150mW and standby is 75mW.

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Why is the NVMe SSD interface inherently more efficient than disk-based protocols such as SATA?

The speed at which the electronics industry moves sometimes masks other developments that are incredibly slow-paced and the conversion of storage I/O protocols from hard-disk-centric to solid-state disks (SSDs) is a shining example. Most SSDs currently employ I/O protocols originally developed for hard disks such as SAS and SATA. We (the industry) did this in the name of expediency. The fastest way to introduce SSDs into the design mix for PCs and servers was to disrupt the supply chain as little as possible. That meant living with motherboards, operating system drivers, interface ports, cables, and even stamped sheet-metal enclosures that had evolved in a world occupied only by hard-disk storage.

That expediency costs us in terms of lost efficiency with respect to SSDs. Take the adoption of the SATA protocol for SSDs as a case study. Where did the SATA storage protocol come from? It is a serialized version of a storage protocol called PATA or “parallel ATA.” Where did PATA come from? The “ATA” part of PATA stands for “AT Attachment” where the “AT” comes from “Advanced Technology,” which was IBM’s name for the second iteration of the original IBM PC, the IBM PC/AT. You know, the version of the IBM PC based on the “advanced” Intel 80286 processor. That PC.

Shugart Technology ST-506 Hard Disk Drive (circa 1980)

What was advanced about the ATA hard-disk interface? It moved the hard-disk controller from an expansion card into the hard drive. Please let that statement sink in. There was a time, in the pre-ATA days, when the hard disk drive was dumb as a rock. It took commands like “step in,” “step out,” “read sector,” and “write sector.” Data supplied to the disk drive had to be appropriately encoded by the external hard-disk controller. This even older, more primitive hard-disk interface came from the original Shugart Technology 5Mbyte (as in “megabyte”) ST-506, the original 5.25-inch hard drive introduced in 1980. Everyone in the hard disk industry—eventually hundreds of vendors—quickly copied the ST-506 interface.

The innovation of the ATA interface—originally developed by Western Digital as the IDE (Integrated Drive Electronics) interface—was to make the hard-disk controller more intimate with the hard drive and the HDA (head disk assembly). This move freed the controller from needing to know how to best control every hard disk ever made. An IDE controller only needs to know about the HDA that it’s welded to.

Because of all this legacy, the SATA protocol still needs to know the basics of hard-disk management. The protocol keeps track of cylinders, heads, and sectors—the atoms and molecules of hard-disk-based storage.. These concepts, of course, are only associated with spinning media—hard-disk storage. They have no meaning for storage based on NAND Flash semiconductor memory. To be used with NAND Flash media, these concepts must first be translated.

Now let’s step back and take a breath here. Let’s remember what we’re actually trying to do at the highest level. At the application level, we actually deal with files. Not cylinders. Not heads. Not sectors. However, the hard disk drive has become so integral to microprocessor-based computing over the past three decades (since the ST-506 drive appeared in 1980) that the translation from files to cylinders, heads, and sectors is buried deeply into our operating systems. With no alternatives for storage, it made perfect sense to meld the file-storage needs of the operating system with the sector-centric world view of the hard disk.

NAND Flash memory does not share that world view.

And that is what brings us (taking the long way home) to NVMe or NVM Express. Leading companies in the storage industry have recognized that the current, popular storage interfaces are too hard-disk centric; they carry too much conceptual baggage that caters to the specific needs of hard disk drives since 1980. Now this baggage is old, but it still serves us well as long as we’re using hard drives. It doesn’t work as well for SSDs. The following diagram shows why.

The block diagram shows the number of translation steps needed to get from the Host CPU to storage in the NAND Flash memory cells. The Host CPU’s parallel bus is serialized and transformed into PCIe, currently the leading bus interface for PCs and many servers. Somewhere, perhaps on a motherboard or perhaps on an expansion card, the PCIe interface is transformed into a SATA interface. The SATA interface then arrives at a SATA controller that manages the attached “hard drives,” whether these drives are actually hard disk drives or SSDs.

At some point, the SATA commands (cylinders, heads, sectors) must be transformed into storage blocks more readily understood by the NAND Flash memories. The NAND Flash memories have their own special needs or peculiarities such as their own block/bank/sectoring scheme, error management protocols including ECC, and wear-leveling algorithms. These peculiarities are handled by the NAND Flash Controller, which then drives the attached NAND Flash memory devices as appropriate.

Translation from PCIe to SATA then to NAND Flash results in a lot of unnecessary overhead, brought on by the desire to slip SSDs into the supply chain with as little disruption as possible.

However, the industry now seems ready to trade off some disruption for more efficiency. The NVMe standard is the result of that change in mindset. Using the NVMe approach, an SSD-based system might look something like this:

To get to this point, changes must occur deep in the operating system. The NVMe specification is now getting close to a year old. Windows and Linux drivers now exist. The revolution is coming.

For more information on the NVMe specification, click here.

Posted in Flash, HDD, NAND, NVM Express, NVMe, SSD | Tagged , , , , , , , | 2 Comments

Do you know the new lessons that SSDs are teaching us?

IT Web recently ran a thoughtful article titled “Storage trends for 2012.” What struck me about this article is that it incorporates some pretty important lessons for anyone designing with SSDs or other forms of NAND Flash storage. Here are some of the lessons I took from this article:

  1. Speed: “…in the second half of 2012, mass adoption of SSDs will reach a tipping point. He says last year saw a steady increase in SSD sales, adding that the increased interest was primarily newly ‘tech-savvy’ consumers and not only tech enthusiasts. The value of adding an SSD to a lagging computer is now in the thoughts of many mainstream consumers.”In other words, a wide swath of computer users and other consumers have tasted the performance benefits of NAND Flash storage and they’re not going back. Consequently, you must now divine the best approach for melding NAND Flash storage into all manner of designs or face the sales consequences to be “earned” from relatively sluggish performance across all consumer, computer, and communications end products.
  2. Capacity: “worldwide sales of tablets are predicted to jump to 326.3 million units by the end of 2015… the high-quality content being consumed on mobile devices will continue to drive storage demand. Consumers who have tablets that do not feature card slots for extended storage are already experiencing storage limitations.”This is actually an old lesson made new by SSDs: there’s no such a thing as too much storage. Video, image, and audio files will grow to fill whatever’s available. Be sure to incorporate some sort of expansion facility into every product to meet customer needs and to pick more dollars up from the table.
  3. Cloud: “… SSDs will gain traction in the data centre market. This market segment has built enough trust in SSD technology to consider the replacement of existing HDDs… High input-output operations per second (IOPs) results means that SSDs are far more suitable for the server environment than HDDs… the push to increase energy savings and optimize performance computing will see SSDs become a priority investment for data centers in 2012.”In other words, the cloud is where it’s at for many large application zones and SSDs give clouds more performance. Time is money.
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Watch out SSDs, here comes the NVM Express!

I was reading an article on the Information Week Web site about using SSDs for accelerating enterprise storage and came across this statement:

“For the most part, the type of SSD that you use in the storage system does not in a significant way impact the performance that you should expect from that tier of storage. The only challenges that form-factor SSDs have are size and power disadvantages vs. other purpose-built designs that look more like memory modules than drives. A flash chip does not need the same volume of space that a HDD needs, does nor does it need the same amount of power. The cost to get to market quickly is a loss of that space and power efficiency.”

That is one of the philosophies behind a relatively new SSD interface spec called NVM Express (NVMe for short). Here’s the NVMe site’s description of the new spec, for comparison:

“The NVM Express specification, developed cooperatively by more than 80 companies from across the industry, was released on March 1, 2011 by the NVMHCI Work Group; now more commonly known as the NVMe Work Group. The NVM Express 1.0 specification defines an optimized register interface, command set and feature set for PCI Express Solid-State Drives (SSDs). The goal is to help enable the broad adoption of solid-state drives (SSDs) using the PCI Express (PCIe) interface.”

You see, SSD interface specs such as SATA and SAS try to make flash look like hard drives. The inherent structure of a hard drive such as sectoring is an integral part of these disk-based specifications because that’s where they trace their roots. Re-using the SATA and SAS specs for SSDs was an expedient thing to do, but the existence of the NVMe spec says “We can do better.”

Posted in Flash, NVM Express, NVMe, SSD | Tagged , , , , , , , | 3 Comments

Hitachi Global Storage unleashes 2.5-inch, 100 to 400Gbyte enterprise SSDs with Intel 25nm SLC NAND Flash

This week, Hitachi GST (Global Storage Technology) announced a new line of 2.5-inch, 100 to 400Gbyte enterprise SSDs, called the Ultrastar SSD400S.B, based on Intel 25nm SLC (single level cell) NAND Flash devices. The endurance specs of the Flash devices plus some intelligent firmware translate into some pretty impressive endurance specs for the drive: 35 petabytes of random write endurance over the drives’ 5-year warranty life. That figure represents a write usage of 19.2 Tbytes/day, every day, for five years. That spec’s going to be like candy for data center managers.

Photo courtesy of Intel Corp

The drives employ a 6Gbps SAS interface and can deliver peak throughputs of 536 Mbytes/sec for reads and 502 Mbytes/sec for writes, also expressed as 57,500 read IOPS and 25,500 write IOPS. The drives also incorporate a self-encrypting option for additional data security.

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Quickly Noted: EETimes on the challenges of testing semiconductor memory for mobile applications. Is testing really a 3D IC “stopper”?

Janine Love at EETimes interviewed Cecil Ho, President of CST (Simmtester.com)—a memory tester vendor, about issues surrounding the testing of semiconductor memory that’s optimized for and aimed at mobile applications. In these applications board real estate and physical volume are critically important, even at the expense of some additional packaging and testing cost. Consequently, you see memories in multichip packages (MCPs) where multiple DRAMs or DRAMs mixed with NAND Flash chips are all placed in one ball grid array package. To date, these memory assemblies have relied almost exclusively on wirebonding.

MCPs presents challenges for component-level testing and these challenges are often cited as “stoppers” for the evolution to 3D assembly. So I found Ho’s answer to one interview question quite interesting.

Love asked Ho:

“What kinds of tests need to be done? Why?”

Ho replied:

“Indeed, MCPs test need not be complicated. Since the DRAM and flash chips are already tested by their original vendor, only a functional test is required to detect assembly error and die handling damages.”

Using my 3D-centric eyeglasses, I’d interpret this response as clearly taking the component-level test issue out of the “stopper” category and into the “solvable” category for 3D memory-stack assembly—but maybe that’s just me.

To read the full EETimes interview with Ho, click here.

Posted in 3D, DRAM, Flash, MCP | Tagged , , , | 1 Comment

Unbelievable but true: bad embedded SSD controller firmware can crash a PC. Next stop—Blue Screen of Death!

According to this article by Anand Lal Shimpi on the eponymous Anandtech.com, several SSD vendors including Intel have recently discovered that it’s possible for an SSD to crash a Microsoft Windows system and invoke the dreaded Blue Screen of Death (BSOD). How? By the SSD spontaneously disconnecting from the system while it’s running. Microsoft Windows really doesn’t like to see itself unexpectedly (or even expectedly) disconnected from the main system drive, wherein resides the operating system’s virtuality. If this should occur, Windows shuts down, displaying a lovely blue screen with some unpleasant warnings on it.

New SSD controller firmware has substantially improved the situation but this episode serves once more to point out how critical to overall system behavior embedded code really is. Flawed embedded firmware can not only bring down a subsystem; it can also bring down an entire system, much to a user’s chagrin.

Incidents like this merely underscore the need to constantly strive to develop less brittle code that can accommodate a wide range of unexpected events. Our system designs are now so complex that we need to become far more aggressive in developing resilient software for a wide range of subsystems and systems.

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Free half-day SSD seminars across North America and the UK

Demartek, a research and analysis firm, will be holding seven free half-day seminars on SSD basics across North America (and one in the UK) during 2012. These seminars look to be pretty basic, so they’re an introduction for people who have yet to study SSDs in depth. The seminars will be taught by Demartek’s founder and president, Dennis Martin. A basic 2-part seminar outline includes:

Part 1:

  • A brief definition of solid-state storage, including DRAM, NVRAM and NAND flash
  • The three types of NAND flash — SLC, MLC and eMLC — will be described including performance and endurance characteristics
  • Key ways solid state differs from conventional magnetic media
  • Using auto-tiering to use solid-state storage cost effectively
  • How built-in compression algorithms can lower the cost per GB ratio of solid-state storage

Part 2:

  • Array-based, in mixed configurations with hard disk drives
  • Server-based using the PCIe interface
  • All-solid-state arrays
  • Caching appliances

Scheduled cities and dates:

  • Tue. Mar. 6 — Los Angeles, CA
  • Thu. Mar. 8 — Minneapolis, MN
  • Thu. Apr. 5 — Toronto, ON
  • Tue. Apr. 17 — Denver, CO
  • Thu. Sep. 13 — San Diego, CA
  • Thu. Sep. 20 — London, UK
  • Tue. Oct. 16 — Washington, DC

More info and registration here.

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Can MLC NAND Flash work in enterprise SSDs? Yes, with the right storage algorithms says Seagate

MLC (multi-level cell) NAND Flash memories provide 2x or 3x the storage for slightly more than the cost of SLC (single-level cell) NAND Flash memories. Consequently, there’s a big economic case to be made for MLC NAND Flash devices in SSDs. The problem with that case is that there’s a big concern: MLC NAND Flash devices have a severely abbreviated write/erase cycle specification. According to a blog published in EETimes by Teresa Worth at Seagate: “Memory cells on an SSD drive have a finite write/erase life before they wear out and the drives become unreliable. 3-bit-per-cell MLC NAND flash can be erased only 100 to 500 times before it goes bad and standard 2-bit-per-cell MLC NAND can withstand only 3,000 to 5,000 Program/Erase (P/E) cycles. In contrast, maximum write/erasures for SLC NAND are 100,000, which made them more reliable.”

It would appear that the severe limitation on Program/Erase cycles would make MLC NAND Flash memories unsuitable for enterprise SSDs, which are used in applications where data reliability is everything (unlike memory sticks, where failure equals disposal).

However, writes Worth, “Newer enterprise MLC technologies, however, are incorporating improvements that enhance endurance and reliability. Advanced media management techniques, such as wear leveling algorithms that dynamically allocate blocks across the entire SSD, help ensure that write activity is spread evenly across the flash, reducing wear and tear on individual cells and extending the useful life of the SSD.”

In other words, an intelligent SSD controller with the right algorithms can make the use of MLC NAND Flash devices far more realistic even in enterprise SSDs. In addition, NAND Flash vendors are now screening MLC devices for endurance and adding on-chip error correction to make these devices far more attractive for enterprise applications. The driver here, of course, is the cost of the memories.

You can read Worth’s full blog here.

Posted in eMMC, Flash, NAND, SLC, SSD | Tagged , , , , , , | 1 Comment

Review of Samsung SM825 Enterprise SSD reveals backup supercapacitors inside

Data security is everything for enterprise storage and that’s why this StorageReview.com teardown analysis of the Samsung SM825 Enterprise SSD is so interesting. Sure, the drive has a sleek aluminum case that’s worthy of a SuperBowl commercial but inside you’ll find four large supercapacitors with enough energy storage (55 seconds worth) to keep the drive going long enough to complete all cached storage write operations. A great idea that will have a big influence on future enterprise server and storage shelf design.

See the full teardown article here complete with a gread board-level shot revealing the bright blue supercapacitors.

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Tom’s Hardware: Even a low-end SSD beats the pants off of a high-end HDD.

Andrew Ku at Tom’s Hardware published a little gem of an article that discusses SSD performance relative to HDD performance in a very interesting and very sane way. Ku writes: “As a point of comparison, a file operation completes 85% faster on a low-end SSD than it does on a high-end hard drive, but there is only an 88% speed difference between a high-end hard drive and a high-end SSD. That why you shouldn’t let less aggressive benchmark results at the low-end deter you from making the switch. You don’t have to have the best SSD to get great performance relative to a hard drive.”

Ku’s article then places 39 SSDs in a 10-tier hierarchy to help you sort out the fastest performers (Tier 1) from the slowest (Tier 10). Just remember, even Tier 10 SSDs are really fast compared to HDDs.

You can read Ku’s full article here.

Posted in HDD, SSD | Tagged , , | 1 Comment

Could the memory business be a major driver for the semiconductor foundry business? MonolithIC 3D’s Deepak Sekar says “Yes!”

Deepak Sekar, Chief Scientist at MonolithIC 3D, has just published a provocative blog with big implications for both the semiconductor memory and foundry businesses. His premise is that even though Samsung has “only” about 7% of the semiconductor foundry business, the company’ semiconductor memory business (Samsung has a big chunk of the memory business, which Sekar estimates at ~40%) gives the company big economies of scale that are easily applied to the foundry business . Here are three of Sekar’s points:

  1. Semiconductor memory vendors live or die on efficiency because it’s a low-margin business. Often, memory margins are described as “razor thin” and occasionally “negative.” Just last week, I was discussing this aspect of the business in a staff meeting in juxtaposition with the foundry business. Now I find a good answer to the quandary in Sekar’s blog: “Samsung’s reputation for high-yield memory products, you would expect Samsung to get good yields in the logic foundry business.  They seem to be delivering on that front. I hear from industry contacts that Samsung is the only manufacturer getting reasonable yields for gate-first high k metal gate products at 28nm.”
  2. Semiconductor manufacturing is capital intensive, so success often hinges on the ability to make large capital expenditures. Because Samsung is not a semiconductor foundry but a large multinational company with diverse product lines in electronics, semiconductors, and myriad other enterprises, the company has a lot more capital to work with than pure-play semiconductor vendors. “Samsung’s capex to revenue ratio for its foundry business is way higher than anyone else,” writes Sekar.
  3. Cost of manufacturing tools is directly affected by purchase volumes. Samsun makes a lot of chips for its own systems businesses (consumer, computer, mobile phone) and it makes a lot of memory chips. So the company buys a lot of semiconductor production equipment. Sekar writes: “The highest volume producer, Samsung, has the lowest raw material costs [based on data from 2003].”

There’s a lot more meat in Sekar’s blog and I suggest you take a look.

Other news about Samsung:

Cadence Collaborates with Samsung Foundry to Deliver Design-for-Manufacturing Solution for 32-, 28- and 20-Nanometer Chip Design




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LeCroy introduces DDR4 Bus and Timing Analyzer at DesignCon 2012

LeCroy’s Kibra 480 DDR bus and timing analyzer now lets you analyze bust traffic on DDR4 interfaces at the board and connector level. It is an evolution from the company’s earlier Kibra 380 DDR3 bus and timing analyzer. (See “How can you be sure DDR2, DDR3, and DDR4 SDRAMs will work properly in your system?”) One of the key technologies in the Kibra 480 is embodied in custom silicon that resides in a self-powered interposer board. This design approach allows the Kibra 480 analyzer to get an instant lock on the DDR4 interfaces signals so that it can capture signal traces even during power up. The analyzer can also help troubleshoot DDR3 memory subsystems with an appropriate DDR3 interposer board.

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JEDEC to hold free server memory forum in Shenzen, March 1

Anyone involved in the development and use of server memory will want to consider the free server memory forum that JEDEC will be holding in Shenzen, China on March 1. Current agenda:

  • Server memory roadmaps and trends
  • DDR4 as enterprise server memory
  • DDR4 power features for servers
  • Real time DDR protocol violation detection and testing

Companies presenting include:

  • Agilent
  • AMD
  • CESI
  • FuturePlus Systems
  • HP
  • Hynix
  • Intel
  • Montage
  • Oracle
  • Samsung

The event will be held at the Crowne Plaza Shenzhen, 9026 Shennan Road in Shenzhen. Admission is free but you must register in advance.

More info here.

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Memcon 2012: Save the date—September 18, 2012 in Santa Clara CA

The date’s official! The 2012 edition of Memcon—the conference devoted to all aspects of semiconductor memory design, manufacture, and use—will take place at the Santa Clara Convention Center on September 18, 2012. So put that date on your calendar now, before something less important comes up (like a significant birthday, wedding anniversary, or award ceremony).

More details to follow shortly.

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Nexsan forecasts five SSD trends for 2012

Storage-system provider Nexsan recently issued a press release predicting five major SSD trends for 2012. They are:

  1. SSD storage system innovations to improve IOPS and reduce end-to-end latency. How? High-speed interfaces such as Infiniband and PCIe, block-level duplication, auto tiering, and caching. (Coincidentally, Intel just this week agreed to buy Qlogic’s Infiniband assets for $125 million. Intel happens to be in the SSD business.)
  2. Better matching of SSD type to application. This trend includes mixing and matching of standard and high-performance drives and tiering of solid-state storage media including DRAM, SLC (single-level cell) NAND Flash, and eMLC (enterprise multi-level cell) NAND Flash devices.
  3. More active system vendor evaluation. Here, Nexsan is saying that system vendors will get more savvy about picking SSDs for specific characteristics that match the intended use of the storage subsystem.
  4. Increased scrutiny in system vendor selection by customers. Nexsan believes customers will get more savvy about selecting SSD-based storage systems.
  5. Encroachment of Multi-Level Cell (MLC) SSDs into the datacenter. MLC SSDs are currently considered to be “consumer-level” drives but the price/capacity ratio is compelling so some companies use them anyway. Nexsan suggests this trend leads to woe through catastrophic data loss.
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Will this be a good year for SSDs? Take the poll!

Earlier in the week, Western Digital’s CEO John Coyne was quoted in the SSD Review as saying that he did not believe that SSDs would play a large role in Ultrabooks. Specifically, he reportedly said:

“I expect ultrabooks to have traditional hard drives, hybrid hard drives and SSDs. We think that the SSD penetration profile will be in very low single digits in a mature ultrabook environment. We see an emerging position for hybrids a little early to develop a view on exactly what percentage of penetration, but we see hybrids as a very compelling alternative on the performance side to solid-state on bang for the buck. We anticipate that in large capacity environments, traditional hard drives will continue to be the compelling solution.”

This remark was widely panned as kicking, er sand, on SSD sales for the coming year.

For a different perspective, we now turn to SanDisk, which conducted an earnings call with analysts yesterday. On this call, EETimes reports that SanDisk CFO Judy Bruner said:

“As the SSD business grows as a percentage of our mix, particularly in the enterprise segment, we believe seasonality will be less pronounced.”

So now we turn to the wisdom of crowds. The Denali Memory Report is giving you a chance to express your optimism (or pessimism) about the chances for SSD sales this year. Please take the poll:

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Elpida prototypes 50nm, 64Mbit, 10nsec Resistive RAM (ReRAM). 30nm production slated for 2013

Elpida, the world’s third largest DRAM manufacturer, just announced successful development of a 64Mbit resistive RAM (ReRAM) prototype chip using a 50nm process technology. Two key specs for this prototype are a 10nsec write speed, similar to DRAM and orders of magnitude faster than NAND Flash memory, and a write endurance rating of more than one million cycles, an order of magnitude better than NAND Flash memory. Both characteristics are essential for any new memory technology that would challenge the dual dominance of DRAM and NAND Flash semiconductor memory.

However, no one is going to get excited about a commercial 64Mbit device when NAND Flash memories and DRAM chips are already available in Gbit densities. So Elpida is planning on using 30nm process technology to build denser (and presumably faster) ReRAM devices with Gbit capacities.

Elpida’s announcement includes Sharp Corp, the University of Tokyo and Japan’s National Institute of Advanced Industrial Science and Technology (AIST), the New Energy and Industrial Technology Development Organization (NEDO), and the University of Tokyo as partners on the ReRAM project. Although it’s not discussed in the press release, according to a presentation made by Deepak Sekar, Chief Scientist at Monolithic 3D, the Sharp ReRAM memory element is based on the movement of oxygen atom vacancies within a TiON layer—a mechanism quite similar to the one described by HP in reference to its memristors.

Posted in DRAM, Flash, Memristor, NAND, ReRAM | Tagged , , , , , | 1 Comment

JEDEC Mobile Memory Summit: The pace quickens and memory standards must keep up

By Scott Jacobson

CES hosted the JEDEC Mobile Memory Summit on January 12th to review the current state of the market for mobile semiconductor memory and to discuss future trends.  It was a full day review of current mobile device trends, the impact of these trends on memory, and how the mobile memory vendors are poised to respond.

The day started with a market overview and social networking has become the top driver for mobile memory requirements, which probably should not be a surprise to you. This trend isn’t expected to slow down soon—you should expect an additional 10X growth in unit shipments by 2020.

Non-volatile mobile memory standards have evolved very rapidly to address these increasing demands through multiple generations of Flash semiconductor memories based on the eMMC (embedded MultiMediaCard) standard and the new generation of UFS (Universal Flash storage) devices.  To appreciate the pressure that the mobile device market has put on memories compared to server memory evolution timelines, mobile memory standards have had to evolve more than twice as fast to keep up with market bandwidth and performance demands.

The demand for increasing bandwidth and performance on non-volatile mobile memory has taxed the performance envelope of the eMMC memory standards.  Specifically, the eMMC memory architecture’s single-channel constraint and low IOPS (I/Os per second) capability fails to meet expected demands for increased performance.  UFS has been designed to answer the call for the increased performance with a dual-channel I/O architecture, high IOPS capability, and lower power requirements than eMMC memory.

The rapid worldwide market evolution in mobile handset design places extreme pressure on the evolution of feature phones. Established smartphone markets—particularly in markets like the US—are experiencing demand for more memory bandwidth and higher device performance whereas emerging markets, like Asia, are more focused on low cost, upgradeable devices.  This dichotomy puts feature phones in between two increasing market segments. The expectation is that this market will come under further increasing pressure in 2012.

Growth in the smartphone market and the demand for increasing performance in this segment drive the adoption of faster memory standards such the LPDDR3 SDRAM standard while the cost-conscious emerging markets are demanding a longer tail to the use of more economical memory such as LPDDR1 SDRAM.

Another significant emerging trend in the mobile handset market is the transition of mobile devices from use as a “consumption” device to the role of “creator.”  The current view is that there is an upcoming inflection point in 2012 where sales of devices that support creative activities will begin to outpace consumption devices, a situation partly driven by the expected growth in productivity focus with new application platforms such as Microsoft Windows 8. Further, by 2013, it’s expected that demands for smartphones optimized for creative activities will drive the evolution of all-in-one devices that satisfy the demands for both consumption and creation.

As this inflection point nears, it will also require more onboard, higher performance memory in every device to support these new creation needs.  To meet these needs, it is expected that by 2013, the memory per device will grow by 2X as compared to 2011 configurations.  In addition to the growth in memory per device, the overall device sales for smartphones and tablets are also expected to grow by nearly 2X in the same timeframe.  These compounding growth rates and their hunger for increased performance dictate that new approaches to onboard memory and storage must be found. UFS memories are poised to answer this call.

The world continues to become more closely connected, always on and increasingly more social.  As this Web 3.0 advance continues, the exponential growth in demand for data continues to put unheralded demands on all parts of the “delivery system” ending in mobile devices.

Keeping up with these increasing demands is not optional; it’s a necessity requiring new approaches in “mobile centric” storage.  Offering lower power consumption, higher performance, low-latency and high IOPS, UFS is answering the call not only for today’s mobile memory needs but also for future needs. UFS is the next generation of non-volatile memory for mobile markets and it’s designed to meet the “social” needs of mobile users around the world.

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Microprocessor Report names Micron Hybrid Memory Cube as “Best Microprocessor Technology” of the year

This week, Microprocessor Report selected the Micron Hybrid Memory Cube (HMC) as the “Best Microprocessor Technology” of 2011. Why? As Tom Halfhill writes:

“Memory cubes promise greater density, lower latency, higher bandwidth, and better power efficiency per bit compared with conventional memories. Early benchmarks show a memory cube blasting data 12 times faster than DDR3-1333 SDRAM while using only about 10% the power.”

He then continues later in the article:

“Even so, memory cubes will not replace commodity DRAMs anytime soon. They will appear first in high-performance servers and supercomputers. Thanks to their high density and power efficiency, future implementations may also be suitable for small mobile systems, such as smartphones and tablets. Over time, as manufacturing costs plummet, stacked memory could eventually supplant conventional DRAM. Therefore, the Hybrid Memory Cube is a crucial technology to watch in the years to come.”

For more technical coverage of the HMC, see:

3D Thursday: Micron’s 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs

Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?

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Samsung packages 4Gbytes of NAND Flash with LPDDR2 DRAM for smartphone and other embedded applications

Samsung has announced that it has started volume production of a combined NAND Flash/DRAM “embedded multichip module” (eMCP). The module combines 30nm-class LPDDR2 DRAM chips (packaged capacities of 256, 512, or 768 Mbytes) with 4Gbytes of 20nm-class NAND Flash in one surface-mount package. The target market for this device is the smartphone market but many other embedded applications can also make use of a device like this. Samsung has been offering such modules for a while. For example, the Denali Memory Report covered the introduction of a similar device that combined DRAM and phase-change memory (PCM) back in May, 2010.

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You say “to-may-to” and I say “to-mah-to.” So how do you say “memristor”? Part 2

A couple of days ago, I noted that Bryon Moyer at Electronic Engineering Journal had interviewed me and quoted me about the recent brush up over the term “memristor” in his article “A Memristor By Any Other Name?”  Moyer wrote:

“Of note, however, is that in many of these, the drifting of oxygen vacancies plays an important role. Sound familiar? It did to me, but, maddeningly, in almost none of the RRAM papers was there any mention of the word “memristor.” Was TiO2 the only “true” (a loaded word, as we’ll see) memristor? Was there some detail that made the other materials not memristive? Or were they also memristive but for some reason no one was mentioning that?

So I looked around for expert opinion to try to referee the situation – which proved harder than I thought (since much of industry focuses on technologies that are manufacturable today – or at least soon, which this is not). I had one conversation with Cadence’s Steve Leibson, who’s been watching the technology.

His view is somewhat practical, by his own admission: he doesn’t really care what you call anything; the question is, is it manufacturable, cost- and power-effective, etc.? If you take RRAM to mean anything that uses a shift in resistance to determine state, then even things like MRAM and phase-change memory (PCRAM) are included.

More interestingly, he alluded to some controversy as to whether what HP found was even a memristor at all – making sure to clarify that this wasn’t his position, just that he was aware that there was some debate; we left it there.”

Now R. Stanley Williams of HP Labs has written a position paper on this tempest in a memristor pot. He writes:

“As a result of his work on nonlinear circuit elements, Chua made an interesting observation. For traditional linear circuits, there are only three independent two-terminal passive circuit elements: the resistor R, the capacitor C and the inductor L. However, when he generalized the mathematical relations to be nonlinear, there was another independent differential relationship that in principle coupled the charge q that flowed through a circuit and the flux φ in the circuit, dφ = M dq, that was mathematically different from the nonlinear resistance that coupled the voltage v to the current i, dv = R di. As a strictly mathematical exercise, he explored the properties of this potentially new nonlinear circuit element, and found that it was essentially a resistor with memory – it was a device that changed its resistance depending on the amount of charge that flowed through the device, and thus he called this hypothetical circuit element M a memristor. This conclusion was independent of any physical mechanism that might couple the flux and charge, and in fact he did not postulate any mechanism at all.”

“This issue was made much clearer in a second paper published with his then student Sung Mo Kang [L. O. Chua & S. M. Kang, Memristive devices and systems, Proc. IEEE 64, 209-223 (1976)]… This 1976 paper showed many other properties of the generalized memristor and also discussed possible examples, but again this was a mathematical exercise that was independent of any physical mechanism at the time. The key result was that any electronic circuit element that displayed a pinched hysteresis loop in its current-voltage characteristic could be described mathematically by the two memristive system equations.”

“Examples of memristors include bipolar and unipolar resistive switches, often called RRAM or ReRAM; ‘atomic switches’; spin-torque transfer RAM devices, phase-change memory devices, and several other systems based on a wide variety of materials and mechanisms [L. Chua, Resistance switching memories are memristors, Appl. Phys. A 102, 765-783 (2011)]. For the most part, we have chosen to use the term memristor to describe the devices in our papers, not because we are trying to impose an ‘HP brand’ (especially since the term was invented by Leon Chua), but because we feel the general term connotes a broader range of applications. ‘RAM’ means random access memory, and that is certainly one application for memristors, but we find that much too restrictive, since they can also be used in a wide variety of other electronic circuits, including logic, FPGAs, and various types of ‘synaptic’ or ‘neural’ applications – memristors are much more than memory.”

“In summary, the memristor was a discovery – it is a rigorous mathematical model that can be used to predict the behavior of a wide variety of physical devices. There have been many developments of different types of memristors, now called by many different names, based on different materials and physical mechanisms, but they are all described by the same general mathematical formalism developed by Chua.”

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You say “to-may-to” and I say “to-mah-to.” So how do you say “memristor”?

Bryon Moyer at Electronic Engineering Journal and I had a discussion a couple of weeks ago about memristors, real and ideal, and resistive RAM. Is there a difference? Does it matter? What is it we’re really looking for, a “true” memristor or a low-cost, nonvolatile way to store bits that’s competitive with NAND Flash memory?

For perspectives on these and other questions, see Moyer’s new article “A Memristor By Any Other Name?

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Is MRAM ramping up to the big time?

Today, MRAM (magnetic RAM) supplier Everspin announced that it expects to close out FY 2011 with a shipment volume that exceeds that of 2010 by more than a factor of three. MRAM combines the thin-film magnetics initially developed for the hard disk industry with the manufacturability of nanometer CMOS. MRAM can deliver DRAM-like speeds (tens of nsec) and Flash-memory-like long-term data retention (on the order of decades) without a significant wearout mechanism. Consequently, cost-competitive MRAM—if and when it appears—presents a real rival to both DRAM and NAND Flash memory.

Currently, MRAM is not cost competitive with DRAM or NAND Flash memory on a per-bit basis, but the technology is already finding niches where its cost and capabilities fit well. One such application is in the use of journal memory in RAID systems. From the Everspin site:

“MRAM performs the write journal or data log function in RAID disk arrays to capture transaction information in real-time so that data can be recovered should a system failure occur. Data logs also capture system conditions and status for remote diagnostics and repair.

Dell uses MRAM as a Raid-On-Chip journal memory solution for its Dell PowerEdge servers and PowerVault Direct Attached Storage (DAS), as well as Dell EqualLogic Storage Area Network (SAN) arrays. In these applications, MRAM provides enhanced data center fault recovery, reduced system downtime and lower total cost of ownership.

MRAM is the journal memory on LSI Corporation’s RAID controller cards featuring 6Gb/s and 12Gb/s SAS storage connectivity. MRAM chips are also included on LSI reference designs for third party RAID cards and RAID-on-Motherboard (ROMB) solutions.”

According to Everspin’s release, it has more than 300 active customers buying more than 100 part numbers in “three major markets” with more than 100 applications.”

Most design engineers these days cannot remember when magnetic memory was the memory of choice for computing equipment but core memory started its rise to prominence in 1953 when core memory was installed in the MIT Whirlwind computer. Magnetic core memory then reigned for 20 years as the king of memory for mainframes and minicomputers. It was even used in small quantities in computing equipment as small as the Apollo Guidance Computer that incorporated 2K words of core memory and the Hewlett-Packard 9100A desktop calculator that used a much smaller 2208-bit magnetic core memory to store the contents of its X, Y, and Z floating-point accumulator/registers. Even the US Space Shuttle employed core memory until 1990 but by then core memory’s usage had dropped to nothing.

The introduction of the Intel 1103 DRAM in 1970 presented the first real challenge to magnetic-core memory. In fact, the DRAM presented such an effective alternative that magnetic core memory essentially disappeared by 1975 (according to Wikipedia). Now, it might be DRAM’s turn.

Note: For more information on MRAM, see:

The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit

Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC NV memory?

Posted in DRAM, Flash, MRAM, NAND | Tagged , , , , | 1 Comment

SSDs as HDD caches to grow like topsy say Intel and IHS iSuppli

Intel has made a significant change in the way its chipsets handle SSDs and the result, according to analyst firm IHS iSuppli, will be a 100x increase in the annual number of drives sold in the PC space between now and 2015. The change Intel has made is to add a feature called Smart Response Technology (SRT) to the firmware for the company’s Z68, QM67, and HM67 chipsets. The firmware can cache both read and write data being retrieved from and sent to the PC’s hard using a relatively small SATA-connected SSD. According to Intel, SRT can automatically boost HDD boot and data-transfer performance substantially with just 20 to 40Gbytes of SSD.

Analysts at HIS iSuppli predict this fabric-level adoption of SSDs as HDD boosters will cause cache SSD sales to jump from less than one million in 2011 to approximately 121 million in 2015. “The majority of cache SSD units will find their way into devices known as ultrabooks” writes iSuppli in its press release for its latest Storage Space Market Brief.

Although SRT works with SATA-connected SSDs from all vendors, Intel has developed an SSD 311 Series of small SSDs that are purpose-built as HDD caching devices using SLC (single-level cell) NAND Flash devices. Intel’s published information states that it chose SLC NAND Flash for its caching SSD design because of better performance and better endurance compared to MLC (multi-level cell) NAND Flash devices. The Intel SSD 311 Series is available in both a conventional 2.5-inch HDD form factor and as an mSATA card designed to be plugged directly into a PC motherboard.

Intel Solid-State Drive 331 Series, mSATA form factor

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Ever get the thrill of seeing a Tesla coil torture an SSD? ioSafe wants to be sure you get the opportunity

One reason for the success of the Robot Wars and Battlebots TV shows among engineers is because they love to see engineered products get destroyed, usually as long as they didn’t have a hand in designing and building them. They can’t turn away. It’s like watching an accident happen. So imagine the vicarious thrill of seeing a Tesla coil drive hundreds of thousands or millions of volts into the case of an ioSafe external SSD at last week’s CES. The company hired Dr. Austin Richards, aka Dr. Megavolt, to do just that.

The point, of course, is that ioSafe SSDs are rugged. They’re waterproof. They’re fireproof (843°C for 30 minutes). They’re “disaster proof” according to the company slogan. However, it’s one thing to say “rugged” and an entirely different thing to demonstrate it. Dramatically and violently. That’s where the Tesla coil comes in.

Yes, the drive survived:

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Crucial updates SSD firmware that allows drives to cruise past 5184 hours

After 5184 hours of active use, users of Crucial SSDs were experiencing intermittent blue screens of death (BSODs). Now the company has released a field-installable firmware update that appears to solve the problem. Check it out here.

As SSDs become increasingly complex, the control of the internal Flash devices and the management of the host interface also becomes increasingly complex.

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IBM’s Almaden Labs sets lower mass bound for nanoscale magnetic storage: 12 atoms

Researchers at the IBM Almaden Labs south of San Jose, CA have experimentally set the lower bound on magnetic storage at 12 atoms. It appears that eight atoms can’t quite cut it. Although the atoms are iron atoms, their antiferromagnetic properties provide the storage mechanism, not the ferromagnetic properties. Because the ferromagnetic properties tend to link adjacent atoms, the antiferromagnetic arrangement used in this latest experiment apparently alternates the magnetic spin directions of adjacent atoms, creating a more stable arrangement. Here’s the byte worth of magnetic storage the IBM researchers assembled using a Scanning Tunneling Microscope, shown in five different states that represent the five ASCII characters in the IBM watchword “THINK”:

It appears that each bit in the byte consists of two rows of six atoms apiece, arranged with alternating magnetic spins. Adjacent atoms in the same row have stable alternating spins while adjacent atoms across rows within the bit have the same spin.

Normally, for a ferromagnetic storage cell in one of today’s hard drives, you’d try to get all of the spins oriented the same way for maximum signal.The antiferromagnetic approach seems to code the bit in the spin sequence rather than trying to orient all the spins in the same way.

For comparison, the densest hard drives currently employ roughly one million atoms to represent a bit. Antiferromagnetic storage promises to improve that density by five orders of magnitude.

Here’s a cool video of the development:

Don’t jump up from your chair just yet and rush out to Fry’s or Best Buy for one of these superdense antiferromagnetic hard drives, however. You won’t be buying hard drives based on this technology soon. Most of the world isn’t ready for cryo-cooled hard drives and you need a 5 Kelvin (–451°F) refrigerator to make this technique work.

See the IBM press release here. http://www-03.ibm.com/press/us/en/pressrelease/36473.wss

Posted in HDD | Tagged , , , , | 1 Comment

New Swiss Army Knife: knife blade, scissors, a nail file, and a 1Tbyte SSD. $3000???

According to this article on www.psfk.com, Swiss Army Knife vendor Victorinox introduced a new pocket knife at this week’s CES with a knife blade, scissors, a nail file, and a 1Tbyte SSD. The SSD is built into a pop-out, clear plastic carrier with an integral graphical LCD to provide status information. The SSD has a USB connector compatible with both USB 2 and 3.0 and eSATA II/III. The SSD also supports 256-bit AES encryption for data security. Estimated retail price: $3000.

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How about a close look at Micron’s incredible shrinking Flash memory?

Chris Ramseyer at Tweaktown was kind enough to notice and snap this photo of Micron’s incredible shrinking Flash memory chips at this week’s Storage Visions event in Las Vegas. The image shows graphically what the numbers tell us intellectually. Starting with 50nm chips, Micron has halved the number of chips needed to store 16Gbytes of information starting in 2006 with eight 16Gbit MLC (multi-level cell) chips. The 34nm node gave us 32Gbit devices; the 25nm node delivered 64Gbit devices; and now the 20nm node is delivering 128Gbit devices. The amount of silicon needed to store 1Gbyte has dropped during this period from 87 to less than 13 mm2.

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High-Speed HDDs versus SSDs: Is there even a question?

Manek Dubash recently published a blog post on the UK ZDNet Web site that discusses the impact SSDs will have on high-speed hard disks in the enterprise storage market. He writes:

“Each approach has its own attractions and dis-benefits, with those relating to the connection type being no different from those of conventional storage. The key attractions of SSDs from a datacentre perspective are of course performance, power and space.

Performance is probably the key issue though. For a virtualised environment, which majors in random rather than sequential access requests, getting enough IOPS from spinning disks is a struggle.”

Dubash then counters with this argument for high-speed hard disks:

“So why would still buy fast spinning storage? It’s still a lot cheaper per GB of course and SSDs do still, I feel, need to fully prove themselves in real world usage. And if you buy into SSDs, you still need a good answer when the CFO comes round and asks why so much is being spent on so little storage capacity, especially given that technology’s well-known propensity to wear out in relatively short order.”

There’s the challenge for SSD, SSD controller, and Flash memory designers. Bring SSD reliability up to snuff and high-speed hard disks are out the door. People will surely pay for performance, but not generally at the expense of reliability.

How will we get there? More ECC? Better ECC in the SSD controller? ECC on each Flash chip as just announced by Toshiba? (See “Toshiba adds 4 and 8Gbit BENAND devices to its SmartNAND lineup”) A replacement for Flash memory? Perhaps MRAM? Perhaps something else?

The economic rewards are high enough to ensure that many of these approaches will be attempted.

As for performance, here’s an Intel video from this week’s Storage Visions conference in Las Vegas that demonstrates the kind of performance gains we’re talking about. It shows an Intel Cherryville SSD versus a 10K RPM hard drive. Guess which drive wins?

This video shows what happens when you combine an SSD with the 6Gbps SATA 3.0 interface. Watch out hard drives!

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SSDs present problems to forensic experts

Sherlock Holmes by Sidney Paget, 1904

Perhaps you’re familiar with the construction of hard disks and SSDs. However, it may not have occurred to you that the radical differences between a spinning hard disk and the stacks of Flash memories in SSDs would present a problem for forensics experts. At least, it did not occur to me. That’s why I found this article by Mike Sheward on the Infosec Resources site interesting enough to blog it here in the Denali Memory Report. Sheward is a network security engineer for a software-as-a-service provider based in Seattle and a researcher at the InfoSec Institute. He’s also worked for the British government. You might want to take a look.

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Need an objective way to evaluate SSD performance? SNIA has one

SNIA, the Storage Networking Industry Association, has just published a White Paper titled “Understanding SSD Performance Using the SNIA SSS Performance Test Specification” as a companion piece to the association’s SSD Performance Test Specification (PTS). As the White Paper’s introduction states:

“A commonly asked question for NAND Flash based SSDs is: “which SSD performs best?” Invariably, the informed answer is “it depends” – this is due to several factors inherent in NAND-based SSDs.”

These factors include:

  1. Device-level factors such as the drive’s condition before the performance test starts, when and how the test sequence is applied, the amount of data transferred each way during the test, the type of data used, etc.
  2. System-level factors including the test platform used, the test program or exerciser used, and the bandwidth of the system-level disk interface.
  3. Architectural factors such as the type of NAND Flash used in the SSD’s construction, the drive’s target use (high read or high write workloads, for example), and the SSD’s warranty life target.

If you need to evaluate SSDs in any context, this SNIA White Paper is an excellent place to start.

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Marvell brews ARM-based native PCIe SSD Controller IC: 88NV9145 handles direct PCIe to NAND Flash I/O for high-performance, low-overhead SSD designs

It looks like 2012 is the year for native PCIe (PCI Express) interfaces to NAND Flash devices. Hot on the heels of the PCIe-based XQD memory card specification from the Compact Flash Alliance (see “Nikon D4 camera and Sony H Series Flash memory cards usher in the era of high-performance XQD cards with PCIe interfaces”) comes the 88NV9145 native PCIe SSD controller IC  from Marvell. The PCIe interface specification is tremendously popular in PC and server designs and is becoming increasingly popular in embedded designs as well. The advantage of a native PCIe-based SSD is that the host CPU can directly communicate with the NAND Flash array instead of using a SAS or SATA disk controller to translate storage accesses into a disk protocol, only to have the protocol translated once more into a protocol that the NAND Flash array understands.

Here’s a block diagram of the Marvell 88NV9145:

As you can see, one ARM-based Marvell 88NV9145 SSD controller IC can control as many as four NAND Flash channels. Once in the PCIe world, it’s relatively easy to use standard, low-cost PCIe hardware such as a PCIe switch to control much larger NAND Flash arrays controlled by multiple Marvell 88NV9145 controllers as seen in this diagram:

For a more in-depth technical analysis of native PCIe SSD designs, see this Marvell White Paper hot off the press.

Posted in Compact Flash, Flash, NAND, PCIe, SSD, XQD | Tagged , , , | 1 Comment

Toshiba adds 4 and 8Gbit BENAND devices to its SmartNAND lineup

Toshiba has just announced a new family of SLC (single-level cell) managed NAND Flash devices dubbed BENAND. The 24nm devices incorporate ECC so that the host processor need not perform that function, which saves time and simplifies the NAND Flash driver software. Another advantage of this managed-NAND device approach is that Toshiba is free to incorporate ever more advanced ECC capabilities in future Flash devices without changing the I/O protocol between the host CPU and the NAND device. It’s a much needed form of future proofing, especially in the embedded space where end products have very long life cycles.

Here’s a Toshiba graphic showing the difference between a system designed to use unmanaged NAND devices and one designed for managed NAND devices:

From the press release:

“Until now, the ECC has been embedded in the host processor and corrected 1 bit per 512 bytes. However, advances in memory process technology require enhanced error correction; more than 4 bit correction per 512 bytes for NAND flash fabricated with 32nm process. For NAND flash memory without ECC fabricated with 32nm and beyond, the controller in the host processor must be changed to secure the required level of correction.”

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Is 2012 the year ONFI 3.0 takes off? Intel, Micron, and Cadence say yes.

The ONFI 3.0 specificationreleased in March, 2011—raises the bar on the interface to Flash semiconductor memory. In particular, it boosts transfer rates to 400 Mtransfers/sec using an NV-DDR2 DDR-400 signaling protocol; it adopts 1.8V SSTL_18 differential signaling on the strobes to boost speed and cut power consumption; and it supports on-die termination (new for the 3.0 version of the ONFI spec). Key semiconductor memory suppliers with their names on the ONFI 3.0 specification include Hynix, Intel, Micron, SanDisk, and Spansion. (Note: ONFI is an abbreviation of the “Open NAND Flash Interface Working Group”)

Intel and Micron jointly previewed a 128Gbit MLC (multi-level cell) NAND Flash device compatible with the ONFI 3.0 specification just last month, based on the companies’ 20nm NAND Flash process technology. As part of that introduction, the two companies revealed that they have started the production ramp on a derivative 64Gbit MLC NAND Flash device and expect a “rapid transition” to the 128Gbit device later in 2012.

So the ONFI 3.0 NAND Flash parts are on the way, which means that it’s appropriate to start incorporating ONFI 3.0 controllers and PHYs into your new SoC designs. Today, Cadence announced immediate availability of a NAND Flash controller IP block and PHY that are compatible with the ONFI 3.0 interface spec. Both the Flash controller and the PHY also support the Toggle 2.0 NAND Flash interface spec and are backward compatible with prior ONFI and Toggle interface specs. Another key feature of this IP offering is support for chip-enable interleaving, which significantly boosts performance in Flash subsystems with multiple NAND Flash devices and achieves as much as 95% of the devices’ theoretical maximum throughput. There’s yet one more piece to this puzzle. Cadence offers complementary verification IP and memory models to ease the design of SoCs using the new ONFI 3.0 interface spec.

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Nikon D4 camera and Sony H Series Flash memory cards usher in the era of high-performance XQD cards with PCIe interfaces

Nikon and Sony have jumped the gun on CES by introducing a new DSLR camera (the Nikon D4) and a new series of Flash storage media (the Sony H Series). These announcements mark the beginning of the XQD Flash card era. The Compact Flash Association announced the XQD memory card format early in December. Physically, the XQD card footprint is slightly larger than an SD memory card and somewhat smaller than a Compact Flash card.

An XQD memory card is much thicker than an SD card; it’s the same thickness as a Compact Flash card.

The big change, however, is that XQD memory cards use the PCIe (PCI Express) interface rather than an existing hard disk or Flash-specific interface protocol. The current XQD interface format calls for a 2.5Gbps data rate, permitting write speeds of 125Mbytes/sec or greater. There’s a plan in place to move to 5Gbps in the future. Of course, this new Flash memory card format has some pretty big implications for SoC designers selecting an interface protocol for Flash cards.

Posted in Compact Flash, Flash, NAND, SD, XQD | Tagged , , , , , | 3 Comments

The return of Memcon in 2012

Under the leadership of Denali Software, Memcon became the single most important event for the semiconductor memory and storage industries. Now Cadence is taking that legacy into the future. Yes, that’s right, Memcon is back for 2012 as a standalone event. I’m not allowed to tell you the exact date yet, but it will be shortly after Labor Day, so you can’t wear white. Oh, and it will take place in the heart of Silicon Valley. Hope to see you there.

Stay tuned to the Denali Memory Report for future announcements.

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Big week for Wide I/O: JEDEC publishes spec while Elpida ships sample 4Gbit parts

Wide I/O jumped closer to being a reality this week with two major announcements. On December 28th, Elpida announced that they were making sample shipments of 4Gbit Wide-IO. (See “Let’s start the new year with a bang! Elpida ships 4Gbit Wide I/O and LPDDR3 SDRAM samples”) Today, January 5th, JEDEC announced  the publication of the Wide I/O standard, which you can download here. (Note: You may need to set up a free account first.)

The Wide I/O SDRAM interface specification is a revolutionary new memory interface technology using a wide array of 512 data pins to connect an SoC to a DRAM and achieves a huge peak bandwidth (more than 100Gbits/sec) using a relatively low 200MHz clock rate (single data rate). Current generation LPDDR2 SDRAM interface technology, by comparison, delivers a peak bandwidth of 34Gbits/sec per die, so the Wide I/O spec delivers roughly three times the memory bandwidth compared with the fastest current LPDDR2 devices. Elpida says that their Wide I/O SDRAM design “…results in approximately 50% less power consumption compared with DDR2 Mobile RAM (LPDDR2), currently the leading DRAM choice for mobile devices, configured at the same transfer rate.”

Wide I/O technology relies on Through Silicon Vias (TSVs), a relatively new 3D IC technology that creates thousands of connections between two die stacked together using vias and solder microbumps to connect the die (3D chip-to-chip stacking). Alternatively, two memory die can be joined with a silicon interposer where the silicon interposer incorporates the TSVs (called the “2.5D” silicon interposer method). Cadence offers design tools and a test methodology for 2.5D and 3D assembly in addition to a Wide I/O SDRAM controller and PHY IP to help you incorporate the Wide I/O interface technology into your next SoC design.

Today’s JEDEC announcement is exciting news for Cadence. We have been investing in Wide I/O technology from an early stage and participating in the JEDEC standardization process. Cadence announced the industry’s first Wide-IO Controller IP solution in March 2011 and then announced our collaboration in producing Wide I/O test chips with ST-Ericsson and CEA-LETI.

For more information on that project, see “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say ‘Tour de Force’?

–Marc Greenberg

Posted in JEDEC, LPDDR2, SDRAM, Wide I/O | Tagged , , , , , , | Leave a comment

Let’s start the new year with a bang! Elpida ships 4Gbit Wide I/O and LPDDR3 SDRAM samples

Two DRAM categories that will shake up mobile product design this year are Wide I/O and LPDDR3. Elpida announced just at the end of the year that it has started shipping samples of 4Gbit SDRAMs with both interface types based on the company’s 30nm process technology. (Just to be clear, both interface types are not, repeat not, available on one device. We’re talking two different next-generation SDRAM families here.)

The Wide I/O SDRAMs have four parallel, 128-bit interfaces that channel 12.8 Gbytes/sec into a host device with 200MHz interface clock speeds, which according to Elpida results in cutting power consumption in half compared to LPDDR2 SDRAMs.

The LPDDR3 interface spec doubles the transfer rate of LPDDR2 (the current SDRAM interface of choice for mobile, low-power  designs) to 6.4 Gbytes/sec per device (with a 32-bit interface) while cutting power consumption by 25% (again, according to Elpida). Use two of these LPDDR3 devices in parallel and you’re up to 12.8 Gbytes/sec.

Elpida plans volume production for these devices in 2012 and both of these chips are destined for 2- and 4-layer 3D memory assemblies.

Note: For more information on Wide I/O SDRAMs, please see “3D Week: JEDEC Wide I/O Memory spec cleared for use.”

For more information on Cadence DRAM controller IP, click here.

Posted in LPDDR, LPDDR2, LPDDR3, Wide I/O | Tagged , , , , | 2 Comments