George Chrysos discussed the Intel MIC (Many Integrated Core) architecture of the Knights Bridge chip (officially called the Intel Xeon Phi coprocessor) at today’s Hot Chips 24 conference and disclosed that it uses GDDR5 graphics memory as the main memory for the manycore part. In fact, the Intel Xeon Phi coprocessor has several (an undisclosed number) on-chip GDDR5 memory controllers. Now GDDR5 SDRAM is high-bandwidth memory generally found on graphics cards, not computing engines. GDDR5 memory supports extremely high data rates in the tens of Gbits/sec using multi-GHz transfer clocks. These SDRAMs also cost more per Gbit than bulk SDRAM, but you’re paying for performance.
And memory performance is exactly what the Intel Xeon Phi coprocessor requires because it contains more than 50 x86 processor cores with an immense thirst for data. Slaking that thirst is why Intel selected GDDR5 graphics SDRAM.
I think this choice has implications for many future manycore SoC designs. The Intel Xeon Phi coprocessor gives us a taste of things to come with other manycore SoC designs. Although the Intel Xeon Phi coprocessor is a homogeneous computing device, the same memory bandwidth issues will surround multicore heterogeneous SoC designs as well. However, I doubt that the solution for these designs will be the use of GDDR5 SDRAM, because that’s not a low-cost approach. Intel can afford to use expensive, high-performance SDRAM because the application, server-centric HPC (high-performance computing), warrants the expense. The Intel Xeon Phi coprocessor replaces even more expensive computing clusters. However most SoCs will need a different sort of approach that doesn’t cost as much.
Wide I/O SDRAM is one possibility, but it requires a more mature 3D IC assembly infrastructure. The Hybrid Memory Cube Consortium represents another such approach, but its target application is HPC, the same application targeted by the Intel Xeon Phi coprocessor.
It’s a problem that will need solving.
For more information on the Intel Xeon Phi coprocessor, see “Zowie! More than 50 x86 cores on the Intel Knights Corner Manycore Coprocessor”
For more information on Wide I/O SDRAM, see “Wide I/O. Don’t leave your SoC without it”
For more information on the Hybrid Memory Cube, see:
- 3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news
- 3D Thursday: Micron’s 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
- 3D Thursday: Hybrid Memory Cube—Does anyone know what’s happening with IBM and Micron?
- Is 2012 going to be another breakout year for NAND Flash and Low-Power Design?