Flash memory endurance, multi-level cells, and process technology

I’ve been following an interesting discussion about Flash memory endurance, multi-level cells, and process technology in the LinkedIn Solid State Storage Group. Yesterday, The Memory Guy Jim Handy stepped in with this comment:

“Flash endurance is the result of disruptions in the tunnel oxide layer. The disruptions come from the stress the high programming fields induce during programming. When enough of these disruptions occur they link together into a short circuit that prevents the floating gate from maintaining a charge.

…The phenomenon that gives MLC worse endurance than SLC is the spreading of the voltage distributions of the multilevel bits as the tunnel oxide disruptions start to trap charges.

What is interesting, though, is that only one bit fails at a time, so a block with eight bit errors must be decommissioned if 8-bit error correction is being used, but this same block performs just fine with higher levels of error correction. 48-bit error correction like that used by Link_A_Media will clearly get very good block endurance out of MLC or even TLC flash.

Really sophisticated controllers use other techniques to manage behavior internal to the flash chip itself, sometimes even changing voltage thresholds and programming algorithms to coax even more life out of each cell.

…The endurance of the flash decreases as the number of bits per cell increases, and it also decreases as the process technology shrinks, forcing controller makers to keep improving their error correction and flash management techniques.”

You might want to take a look at the whole discussion, if you’re a member of LinkedIn.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in Flash, NAND and tagged , , , , , . Bookmark the permalink.

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