Test your system design for DDR4 JEDEC compliance with this $4500 ‘Scope add-on

Agilent has just announced a compliance test application for DDR4 SDRAM system designs. The $4500 Agilent N6462A DDR4 test application accelerates bring-up and debugging of DDR4 SDRAM-based systems by automating a bevy of physical-layer I/O testing with the company’s 9000 and 90000A, 90000 X-Series, and 90000 Q-Series oscilloscopes. The automated test roster includes compliance testing of clock jitter, electrical, and timing measurements in accordance to the JEDEC DDR4 SDRAM specifications from DDR4-1600 through DDR4-3200 speed grades. Automated tests include:

  • Single-ended and differential electrical parametric tests
  • Read and Write tests
  • Timing tests
  • Clock-timing tests

Note: Agilent will be exhibiting at Memcon next month. For registration details, click on the banner over there to the right of this blog post.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in DDR, DDR4, DRAM, SDRAM and tagged , , , , , . Bookmark the permalink.

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