Save the date: JEDEC DDR4 Workshop, Santa Clara, CA. October 30-31

JEDEC is sponsoring a 2-day DDR4 workshop that should interest anyone planning on using DDR4 SDRAM in next-generation designs.

Day 1:

  • DDR4 vs DDR3: Comparison Matrix
  • Why migrate to DDR4
  • Power-on, initialization, and training
  • Read/Write and refresh operation review

Day 2:

  • Manufacturability and reliability issues
  • DDR4 power-saving features, modes, and techniques
  • DDR4 3D arrays
  • DDR4 module outlook

The event takes place on October 30-31 at the Santa Clara Marriott in the center of Silicon Valley. Click here for more details.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in DDR4, DRAM, SDRAM and tagged , . Bookmark the permalink.

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