Want the latest scoop on DDR4 DRAM? Here are some technical answers from the Micron team of interest to IC, system, and pcb designers

DDR4 SDRAM is on the way. Just his month, Samsung announced sampling of its 16Gbyte DDR4 SDRAM RDIMMs (registered DIMMs) based on its 30nm-class DDR4 SDRAM chips. Production is slated for next year. Micron has announced plans for volume DDR4 SDRAM production even earlier, late this year. The design of SoCs and other sorts of devices with integrated DDR4 memory controllers is already well underway. I recently gave some questions about DDR4 SDRAM to the memory guru at Cadence, Marc Greenberg and he sent the questions along to Micron. Andreas Schlapka, Senior Product Line Manager at Micron Technology, and his team at Micron supplied these interesting answers:

Why did we need a DDR4 spec? Couldn’t we extend DDR3?

[The need for] increasing memory speed has been a challenge to the DRAM industry for decades. Rising energy costs and the focus of mobile power consumption make memory power and energy consumption important factors as well. DDR3 has been extended beyond its initial capabilities by adding higher data rates (1866 and 2133 Mbytes/sec) and reducing the [supply] voltage (from 1.5V to 1.35V). DDR4 is now enabling the industry to go well beyond the extension of DDR3—with data rates to 3200Mbytes/sec and an operating voltage of only 1.2V.

What three things do IC designers most need to know about DDR4 to build first-time-right SoCs that can control DDR4 SDRAM?

The top three topics the designers need to take into account for with DDR4 memory are:

  1. VrefDQ Calibration, new addressing schemes and the power saving features.  DDR4 requires that the VrefDQ calibration be performed by the controller.
  2. There are several new address schemes which include bank grouping to maximize effective bandwidth, ACT_n activate pin to replace RAS#, CAS#, and WE# commands, PAR and Alert_n for error checking and DBI_n for data bus inversion.
  3. There are a multitude of new [DDR4] power-saving features including Low Power Auto Self Refresh, Temperature Controlled Refresh, Fine Granularity Refresh, Data Bus Inversion, and CMD/ADDT latency.

What three things do board-level designers need to know about DDR4 that they didn’t need to know with DDR3?

The first topic that board-level designers need to account for is the new power supplies, VDD/VDDQ = 1.2V and VPP = 2.5V (wordline boost). The next difference is that VrefDQ is supplied by the DRAM internally while VrefCA is supplied by the board. And lastly, DQ pins are terminated high via pseudo open drain I/O unlike the CA pins that are center-tapped to VTT (like DDR3).

How far will DDR4 take us and for how long?

The final details of the DDR4 standard especially on the module definition are soon to be closed in JEDEC. Major DRAM suppliers have first samples available and [design] work at enablers and OEMs is ongoing to ramp up the first systems in early 2013. The volume cross over between DDR3 and DDR4 is expected in 2015. Based on the historical lifetime for a DRAM technology of about 4 years, any DDR4 successor would need to become available 2017, with volume cross over in 2019. But so far it’s unclear what this new technology could look like. Once the standardization work on DDR4 is done, the industry will focus on next steps and evaluate concepts like HMC (the Hybrid Memory Cube) for the next-generation mainstream DRAM.

For more information on DDR4 SDRAM, see these earlier blog posts:

The DDR4 SDRAM spec and SoC design. What do we know now?

Samsung starts to sample 16Gbyte DDR4 LRDIMMs using 30nm-class DDR4 memory chips

Micron samples DDR4 module at 2400Mtransfers/sec. Production pegged in 2013

Memory to processors: “Without me, you’re nothing.” DDR4 is on the way.

JEDEC releases more details about DDR4 SDRAM spec. Want to know what they are?

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
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