Yesterday, Micron announced volume production of a new memory device containing one 1Gbit PCM (phase-change memory) die and one 512Mbit LPDDR2 SDRAM die. This morning, I had a conversation about this new device with Philippe Berge—Senior Director of the NOR, PCM, e.MMC Business, Wireless Solutions Group at Micron Technology—who gave me some additional technical details.
The first question I asked was about whether or not the device had a part number, which is simply an easier linguistic handle to use when writing about the memory component. Because the device is targeted at the high-end of the feature phone market and is not a catalog part, it doesn’t have a part number that Micron cares to publicize. So I’ll continue to refer to it as “the device” in this blog.
Berge said that this announcement of a 1Gbit PCM/512Mbit SDRAM combo device is the first of many such high-volume devices aimed at feature phones and other mobile devices. The end-product targets for this device and others in the family are the sockets for NOR Flash memory and SDRAM in feature-phone handsets. The device that Micron announced yesterday is for high-end feature phones. According to Berge, smaller-capacity devices in the family will follow and Micron will start to discuss the use of these devices in other markets next year.
The technical specs for the newly announced memory device are fairly interesting. The PCM die and the SDRAM die share an LPDDR2 interface. That means that the PCM die employs the LPDDR2-NVM interface protocol. The two die reside in the device package as stacked die, with wire-bonded interconnect. This is a common form of 3D IC assembly that’s long been in use for mobile phone handset components to reduce component footprint and therefore printed-circuit board area. In this case, the design also reduces end-product manufacturing cost because the application processor needs only one interface and possibly only one memory controller to communicate with the PCM device and the SDRAM. There are also fewer printed-circuit traces to deal with using this approach.
The device’s LPDDR2-NVM interface employs 400MHz, double-data rate transfers so the supported memory bandwidth is fairly high. One important end-product characteristic aided by this high bandwidth is boot time. It simply takes less time to get the boot code out of the PCM compared to NOR Flash memory.
PCM brings two additional performance enhancers to the party. The first is the elimination of the erase cycles required by NOR Flash memory when writing to the non-volatile memory. PCM is bit-alterable without the need for an erase cycle. This attribute speeds write times and simplifies the associated software.
The second performance enhancer is the PCM’s write speed, which is 10Mbytes/sec in this new Micron device. NOR Flash typically supports write speeds of less than 1Mbyte/sec. That’s at least a 10x difference, depending on the NOR Flash device used for comparison.
Finally, I’ve written in the past about a possible problem with PCM self-erasure due to ambient temperature. The new Micron device’s temperature rating is -25 to +85°C. Self erasure is not an issue for this device, according to Berge.
For the previous blog entry about the Micron announcement, see “Micron announces volume production of PCM/DRAM multichip packaged memory”.
For more information on the LPDDR2 and LPDDR2-NVM interfaces, see “LPDDR2: The new mainstream memory for embedded and mobile applications?”
For additional information on previous PCM announcements, see “Numonyx 128-Mbit serial- and parallel-I/O PCM non-volatile memories now available in volume,” and “Samsung announces imminent release of a multichip module integrating DRAM and PCM for Smartphone applications”