Want a quick and dirty overview of the new JEDEC LPDDR3 spec? EETimes serves it up

Kristin Lewotsky has just published an LPDDR3 SDRAM interview with Huong Vuong, Chairman of the JEDEC JC-42.6 Subcommittee for Low Power Memories. Here are the salient points from the interview, in my opinion:

  • The purpose of LPDDR3 is to increase LPDDR2 performance from 1066Mbps to 1600Mbps with minimal changes to the aging LPDDR2 spec
  • Two key additions made to the spec are write leveling and C/A (command/address) training
  • LPDDR3 also lowers the I/O capacitance limit to improve timing
  • Work has already started on the LPDDR3E spec that will increase memory bandwidth and the LPDDR4 spec with the intent of doubling LPDDR3 performance

Write leveling and C/A training allow SDRAM memory controllers to compensate for signal skew between the controlling SoC and the LPDDR3 SDRAM, which helps to ensure that data input setup and hold times and command/address input timing requirements are met at these higher transfer rates.

Note: For a quick bring-me-up-to-speed tutorial on LPDDR2, see “LPDDR2: The new mainstream memory for embedded and mobile applications?” and “State-of-the-Art in Low-Power Memory: Denali’s MemCon”.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in LPDDR2, LPDDR3, LPDDR3E, LPDDR4, SDRAM and tagged , , , , , , . Bookmark the permalink.

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