Earlier this month, JEDEC published the LPDDR3 specification for the next generation of low-power SDRAM that will be used in mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks. The LPDDR3 supports memory transfer rates of 6.4Gbits/sec—12.8Gbits/sec for a dual-channel configuration—and the DDR4 spec support memory transfer rates of 3.2Gbits/sec per pin. Now, the DDR PHY Interface (DFI) Group has announced a revision of the DFI specification (version 3.1) that adds LPDDR3 and DDR4 capabilities to the existing specification. The DFI spec defines a standard interface between DDR memory controllers and the PHYs that communicate directly with the associated SDRAM chips.
Coincident with the DFI announcement, Cadence has announced DDR controller and DDR PHY design IP and verification IP that conforms to the DFI and JEDEC specifications.