Cadence introduced an NVM Express (NVMe) controller subsystem this week. The Denali Memory Report and the EDA360 Insider have covered NVMe developments several times already (see below for the links) and it’s clear that one way to maximize SSD performance is to connect the SSD to the host CPU through a non-limiting interface. Enter NVMe, which layers storage-centric protocols on the hugely successful and very fast PCIe interface.
The following diagram shows the relationship among the elements of the Cadence NVMe subsystem, which appears in the lower left quadrant of the image:
An NVMe controller implements the storage-centric NVMe commands in the subsystem and passes the resulting command and data streams to a PCIe controller for further formatting. The resulting data stream goes out over the PCIe PHY and data returns through the reverse path. Appropriate firmware manages the overall operation.
Why not combine the NVMe and PCIe controllers into one block? That question goes to the heart of IP-centric design and good practice for IP reuse. The NVMe specification leverages the well established PCIe protocol for its transport layer and the Cadence NVMe subsystem implements that transport layer with a proven PCIe controller and PHY. The subsystem integrates the NVMe controller with the existing PCIe hardware in the same way that the NVMe specification integrates the NVMe layer with PCIe. The Cadence NVMe subsystem also includes Verification IP to aid in system integration.
For more information on this subsystem, see Richard Goering’s blog post titled “How IP Subsystem Will Speed NVM Express (NVMe) Adoption” in his Industry Insights blog.
For more information on NVMe, see the following blog posts in the Denali Memory Report and the EDA360 Insider:
- Watch out SSDs, here comes the NVM Express!
- Intel’s Knut Grimsrud explains how to get another 20x improvement in SSD performance
- Why is the NVMe SSD interface inherently more efficient than disk-based protocols such as SATA?
- NVMe storage-optimized PCIe interface gets an Interoperability Lab at University of New Hampshire