Simple three-bar graph explains all the engineering economics of 3D memory you need to know

The January IEEE Spectrum contained an article titled “3-D Chips Grow Up.” The article reproduced a simple Samsung bar graph about the very real advantages of 3D memory interconnect. That graph tells you all you need to know about why there’s a push to get 3D IC assembly off the ground, at least for memory. Bandwidth up 800%. Power consumption down 50%. Real estate on the pcb reduced by 65%. (Thanks to David Thon for the tip.)

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 3D, SDRAM and tagged , . Bookmark the permalink.

2 Responses to Simple three-bar graph explains all the engineering economics of 3D memory you need to know

  1. Erica says:

    And latency? Increased 100x for writes and 1000x for reads. Flash is dead.

    • sleibson2 says:

      Sorry, I can’t agree about Flash being dead, Erica. There are a lot of technologies that aspire to killing NAND Flash. STT-MRAM, Memristor, and ReRAM just to name three. But none of them are in volume production yet. Flash ain’t dead. Flash lives.

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