Multicore, the Memory Wall, and Numerical Compression—FREE Webcast now available

Last month I posted a review of Al Wegener’s terrific IEEE Computer Society presentation at Cadence titled “Multicore, the Memory Wall, and Numerical Compression.” (See “Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?”) Now, you can see the actual presentation as a recorded Webcast, for free. Wegener is the CTO, chairman, and founder of Samplify Systems and he has a firm grasp of the issues surrounding processor-memory and multicore-memory access. This information is an essential part of any sound processing architecture and now you can view it for free.

Click here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in DRAM, SDRAM, SRAM and tagged , , , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s