Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including wafer fab process nodes, backend interconnect, and packaging technologies.
Qualcomm has been working on 3D IC technology development projects to help prepare the company for a 3D future. “3D DRAM stacking has started—it’s shipping in products because it has maintained the bit density/cost ratio,” said Yu. The next thing that will happen, he predicted, is memory stacked on logic. Yu then specifically mentioned Wide I/O and Wide I/O 2 SDRAM, which deliver more memory bandwidth at lower operating power than DDR memory. (See “3D Week: JEDEC Wide I/O Memory spec cleared for use” and “Where does LPDDR3 SDRAM fit in the low-power memory universe? How about Wide I/O SDRAM?”.)
The Holy Grail, said Yu, is full 3D IC assembly that fits RF, memory, power, logic, and sensor die into one package. “It will take a lot of hard work to make this happen,” he predicted. “The thermal envelope is perhaps the biggest limited factor, but power consumption is another major consideration,” Yu continued, “Batteries aren’t getting better. However, if we don’t make the cost structure right, it’s not going to happen for cellphones.”
“And cost drives everything,” he added, making that fact very clear with one slide. The slide showed two curves: GSM mobile handset unit cost over time and GSM mobile handset sales volume over time. “Once we dropped below $200,” said Yu, “worldwide sales really took off” referring to a sharp knee in the sales-volume curve that led to billion-unit annual sales. That’s why we need low-cost 3D IC assembly, continued Yu. “Cost opens the door to sales volume.”
Denali Memory Report 
informative article