System designs employing DDR3 SDRAMs present many new pcb design challenges compared to DDR2. DDR3 clock, address, and control lines employ a new fly-by topology; setup and hold times need to be just right because there are reduced timing margins thanks to the higher DDR3 clock speeds. If you are facing the challenge of designing a pcb populated with DDR3 SDRAM DIMMs, you need not face that challenge alone. You can take a full 1-day workshop that will successfully lead you through the complex design maze and help you reach the end of the maze with a pcb that works.
The one-day workshop is part of CDNLive! EMEA taking place in Munich on May 14-16. The full-day DDR3 pcb design workshop takes place on Monday, May 14. Seating is limited, so you will want to register now before all the seats are gone.