A possible roadmap for Wide I/O that leads to 2Tbps of SDRAM memory bandwidth—per device

Cadence Product Marketing Director Marc Greenberg—one of the speakers at last week’s EDPS conference held in Monterey, California—spoke about why the Wide I/O SDRAM is probably the “killer app” that unleashes 3D IC assembly into the mainstream. Richard Goering has already written a blog about most of Marc’s talk (see “EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs”) leaving me with little to add but a discussion of a potential Wide I/O roadmap that leads from the present JEDEC standard that delivers 100Gbps of memory bandwidth through a 512-bit interface running at 200M transfers/sec to 2Tbps in the future. (It’s actually four 128-bit data interfaces operating in parallel.)

Now Marc carefully pointed out that he was not representing JEDEC during his talk, so the following graphic is not an official roadmap. Nevertheless, here’s a potential roadmap for the Wide I/O 3D technology:

If you look at this graph, you might first wonder why the current Wide I/O standard is so slow. Single-data-rate transfers at 200M transfers/sec extract “only” 1Gbps of bandwidth from the Wide I/O data interface. The all-too-simple answer is “power.” The current JESD229 Wide I/O Single Data Rate (SDR) JEDEC standard was designed to deliver twice the bandwidth of LPDDR2 memory at the same operating power specifically for power-constrained mobile applications. (See “3D Week: JEDEC Wide I/O Memory spec cleared for use”.)

Obviously, advanced semiconductor memory process technology can go faster than 200MHz, single data rate. It already does for several SDRAM device classes including DDR2, DDR3, DDR4, and LPDDR2/3. So Greenberg’s graph, reproduced above, states the less-than-shocking news that Wide I/O SDRAM transfer rates could (likely will) increase and could adopt the well-accepted double-data-rate transfer mechanism—at the expense of operating power.

The above timeline shows the first step up in transfer rate might be to use a 266MHz transfer clock resulting in 532M transfers/sec using DDR signaling, nearly tripling the bandwidth to 266Gbps. It’s also possible to consider bumping the transfer rate to 2133M transfer/sec using a 1066MHz clock—still well within the speed envelope of today’s semiconductor memory processes. Further into the future, the rate could again jump to 2Tbps.

What’s amazing is that these transfer rates are all for individual devices.

What’s even more amazing is that we will certainly figure out something interesting and exciting to do with this extra bandwidth.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in DDR, DDR3, DDR4, DRAM, SDRAM, Wide I/O and tagged , , , , . Bookmark the permalink.

2 Responses to A possible roadmap for Wide I/O that leads to 2Tbps of SDRAM memory bandwidth—per device

  1. DDR4 is on the horizon. The first development and validation tools have just been announced. http://www.agilent.com/about/newsroom/presrel/2012/10apr-em12054.html Expect to see real DDR4 systems in 2013

  2. Pingback: 3D Thursday: The low down on low-power CPU-memory connections from EDPS | EDA360 Insider

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