Need fast, low-power, small, dual-ported embedded SRAM for your SoC designs? Memoir Systems Renaissance 2X memory compiler lets you pick all three: power, performance, and area

SoC designers use a lot of on-chip dual-ported SRAM, typically as an interface buffer between two major logic blocks. IP startup Memoir Systems has just introduced four memory compilers that produce a range of dual-ported embedded SRAM blocks and these memory blocks outperform conventional dual-port SRAM IP blocks in terms of power, area, and speed. That’s right, you get to pick “all of the above” for your dual-port RAM requirements. The trick here is to use existing, proven single-port memories generated by “industry standard” memory compilers and then stitch these memories together with logic to produce what Memoir calls “algorithmic memory” as shown in this graphic:

The diagram shows several standard single-port SRAM arrays (labeled “1P,” with 12 such 1P blocks shown in this example) surrounded by Memoir’s algorithmic memory logic to form one large dual-ported SRAM block. In this case, the diagram shows two independent memory ports leading into and out of the memory block, making this design a full dual-ported SRAM.

This approach obviously adds overhead—about 15% for the algorithmic memory logic and the duplicated address decoders and data multiplexers. However, that 15% overhead is on top of the area needed by the single-port SRAM blocks. Compared to existing dual-port SRAM designs, Memoir Systems’ approach saves area. How much? Take a look at this chart:

The top curve in this chart shows memory density for single-port SRAM based on a 6T (six-transistor) memory cell. The bottom curve shows memory density for dual-port SRAM based on an 8T memory cell, which is typical of dual-port SRAM IP. For a variety of reasons, the bit density for conventional dual-ported SRAMs is about half that of single-ported SRAMs. The middle two curves show the range of densities you get from the four different Memoir Systems Renaissance 2X memory generators. These densities are closer to those for single-ported SRAMs than for conventional dual-ported SRAMs.

Why four memory generators? Each of the four generators provides a different type of dual-ported memory so that you can trade off capability versus area and speed. The four generator types produce:

  • Full dual-ported memory (two ports, each with read/write capability)
  • Dual-ported memory with one read and one write port (for unidirectional buffers)
  • Dual-ported memory with one read/write and one write port
  • Dual ported memory that can perform two simultaneous reads or one write

The Memoir Renaissance 2X memory generators use existing “industry standard” single-ported memory cells available from other IP vendors and then stitch these cells into a logic matrix created by the Memoir memory generators. The result is an IP block that presents two SRAM interfaces to the other logic on the SoC.

So how real are the claims of better area, power, and speed. Glad you asked. Here are the curves:

This chart shows you the area savings relative to a conventional dual-port SRAM IP design. As you can see from the curve, a full dual-ported memory using the Memoir algorithmic memory generator is not area competitive with conventional dual-ported SRAM with memory capacities below about 300Kbits. However, by the time you reach a couple of Mbits in capacity, you are better off to go with the Memoir approach in terms of area. But this is where the other flavors of dual-ported SRAM come into play. If you don’t need for both ports to be full read/write ports, then you are always better off—in terms of area—with the Memoir algorithmic memory approach as shown by the other curves in the chart.

How about power consumption? Here’s the curve:

The top curve is for conventional dual-ported memory. Note the knee in the power curve at 400MHz for conventional dual-ported memory. Now note that there are no such knees for the Memoir algorithmic memory. Based on this one data point (1Mbit dual-ported memory implemented in 40nm), it appears that you are virtually always better off from a power-consumption perspective using the algorithmic memory over conventional dual-ported memory.

Finally, here’s the clincher from my perspective:

This chart plots memory speed versus area for a 1Mbit dual-ported memory implemented in a 40nm process technology. Note that the conventional dual-ported SRAM starts to need a lot more area at 400MHz, which explains the steep rise in power at 400MHz shown in the previous chart. Also note that the conventional dual-port memory tops out at about 500MHz. It can’t go faster. However, Memoir Systems’ algorithmic memory, which is built from conventional single-ported SRAM blocks, extends the operating range of dual-ported memory to 700MHz (again assuming 40nm). There are a lot of SoC designs that need that extra speed. Perhaps yours is one of them.

So you can indeed get advantages in power, area, and performance from this technology.

One final note: This announcement from Memoir Systems discusses four 2-port memory-block generators in the company’s Renaissance 2X family. However, the technology is not limited to creating dual-ported memories. On a consulting basis, Memoir Systems has already been working with clients on creating memory IP blocks with as many as eight ports.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
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