Upgrading your mobile or low-power SoC to LPDDR3? Got the right IP? You’ll need it to get maximum performance at minimum power

LPDDR3 is JEDEC’s next click on the low-power LPDDR SDRAM standard for mobile, portable, and other low-power devices. According to the JEDEC Web site, the LPDDR3 standard is still in development but the technical specs of the early devices announced by Elpida at the end of 2011 are impressive:

• 6.4Gbytes/sec for one memory channel at 800MHz (twice the transfer rate of LPDDR2’s 3.2Gbytes/sec, when clocking at 400MHz)
• Approximately 25% less power consumption

Samples of LPDDR3 SDRAMs have already shipped (see “Let’s start the new year with a bang! Elpida ships 4Gbit Wide I/O and LPDDR3 SDRAM samples”) so the time to start designing SoCs that will use LPDDR3 memory is already upon us.

To do that, you’ll need a variety of IP: an LPDDR3 memory controller, an LPDDR3 PHY, simulation models for these two pieces of design IP, LPDDR3 verification IP and LPDDR3 memory models, and your pc board designers would probably appreciate a design-in kit to help connect the resulting SoC to the high-speed LPDDR3 memory on the circuit board. All of these elements are available in the LPDDR3 IP portfolio announced today by Cadence.

Of particular note: the Cadence DDR Memory Controller has been upgraded to deal with the particular needs of LPDDR3 memory.

Cadence DDR Memory Controller Block Diagram

The upgrades to the Cadence DDR Memory Controller all relate to improving overall DDR memory bandwidth and latency and include:

• Improvements to write-reordering and write-latency rules
• Taking advantage of Additive Latency to streamline commands to the SDRAM
• Tuning improvements to read/write command grouping
• Traffic-based control of the SDRAM’s autoprecharge mode

It’s interesting to think about where these improvements to the DDR Memory Controller came from. Like all good design teams, the designers of the Cadence DDR Memory Controller learn from a close collaboration with their customers. SDRAM protocols have become extremely complex, so test cases with command sequences help to exercise many different controller scenarios based on traffic from the various data sources and sinks in the SoC. A bakers dozen of tough test cases supplied by a customer highlighted places where the design team could eke out even better bandwidth and latency performance from the DDR controller-SDRAM combination.

Good bandwidth performance got even better. Everyone using the DDR Memory Controller benefits.