Last week, Agilent ran a seminar in Milpitas, California. The first of three subseminars was about memory technology with an excellent overview of the state of memory technology today. It was presented by Gordon Getty, an Agilent Application Engineer based in Santa Clara, California. Getty’s seminar segment on semiconductor memory started with this attention-getting statement:
“Memory technology has hit a wall due to physics limitations and that has implications for your designs.”
Because of this wall, which relates to speed and power, memory technology has been bifurcating to meet the opposing needs of PCs and servers on one side, mobile and portable devices on the other. PCs and especially servers need speed at almost any price. Power consumption is a secondary consideration. Mobile applications need fast memory with low power consumption. Consequently, the semiconductor memory industry has been and is evolving different interface standards to meet the divergent needs of these application markets.
Getty divided semiconductor memory into six major categories and tied each category to typical applications:
- DDR – PCs and servers
- GDDR – Graphics boards and embedded systems (in the future)
- LPDDR – Mobile and embedded
- QDR – Specialty memory (QDR Consortium)
- NAND/NOR – Semiconductor Flash for code and data storage
- e-MMC/SD – Managed Flash memory for mass storage
Getty then ticked off each category with some top-line DDR characteristics:
- Currently at 2133 Mtransfers/sec, heading towards 2.3 Gtransfers/sec
- VDD: 1.5, 1.35, 1.25V
- 3D stacking
- 2.4Gtransfers/sec heading toward 3.2Gtransfers.sec
- Big physics challenges forcing a transition like PCI to PCIe
- Memory still resides in a parallel world, so DDR4 isn’t going serial, it going point-to-point
- 6Gbps per pin heading to 8Gbps per pin in 2012
- Point-to-point connections
- LPDDR2: 800Mbps per pin heading to 1067Mbps per pin
- LPDDR3: 1600Mbps
The increase in the rate of speed for per-pin memory connections is leveling off due to the physics of the situation, said Getty as he showed a slide with the signature curves showing a technology reaching maturity.
“Memory is finally boxed in by physics,” he said. Memory interface designers must make compromises in per-pin transfer rates and the number of parallel data pins in the interface. As physics enforces its laws, the number of data pins tends to go up but there are limits there too. More pins means more manufacturing issues and reliability starts to drop.
Does that mean we’ve hit a brick wall? Perhaps not, said Getty. It’s possible for memory to take the serial route the way the parallel PCI interface has evolved into the PCIe serial interface spec, which initially supported 2.5Gtransfer/sec per pin and now has been extended to 8Gtransfers/sec per pin. With new coding, PCIe at 8Gtransfers/sec per pin delivers four times the data rate of the 2.5Gtransfer/sec rate.
Getty then said that the key system-level memory design challenges are:
- Increasing system failures due to more pins and higher speeds
- Standards compliance (need to build this in from the start)
- Signal integrity (increasingly critical as transfer rates rise)
- Timing margin
- Probability (for physical testing of manufactured systems)
Agilent presented this seminar because it offers measurement and analysis tools for a variety of memory interface standards.
Note: Cadence offers design IP, memory models, and verification IP for a variety of memory devices.