More DDR4, DDR3, and 3D IC technical details from ISSCC, courtesy of memory analyst and expert Jim Handy

Semiconductor memory analyst and expert Jim Handy has just published an overview of some memory papers given at last week’s ISSCC. Handy’s article on the ElectroIQ web site supplements some of the previous Denali Memory Report blog entries published earlier this week. Among Handy’s tidbits:

  • Samsung’s paper highlighted the clock circuitry in the company’s 39nm implementation of a a 4Gbit DDR4 SDRAM. The memory chip performs parity generation and checking on the address and command lines and uses CRC generation and checking on the data.
  • Hynix described a 38nm implementation of a 2Gbit DDR4 SDRAM that runs at 1.2V. The chip has a die size of 43.15mm2 and power consumption is said to be about 50% less than the equivalent DDR3 SDRAM even though the DDR4 and DDR3 memory cores operate at the same frequency. That says a lot about the on-chip peripheral circuitry and the I/O schemes.
  • Hynix also described a DDR3 SDRAM built with 23nm process technology resulting in a die size of 30.9mm2.
  • Hynix described a special clocking scheme for TSVs (through-silicon vias) that aligns the clocks for all SDRAMs in a multi-die 3D stack.

You’ll find Handy’s full article here.

For earlier Denali Memory Report blog posts connected to last week’s ISSCC, see:

SanDisk shows 128Gbit, 3-level cell NAND Flash memory chip at ISSCC. Is 20nm (or 19nm) here, so soon?

SanDisk’s founder and retired CEO Eli Harari says that the future of SSDs, computer memory, and everything else belongs to memristors at 11nm

Operational DDR4 SDRAM prototypes appear at ISSCC

For more information on the Cadence DDR4 and DDR3 SDRAM controller IP, click here.

For more information on the Cadence DDR4 and DDR3 PHYs, click here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in 3D, DDR3, DDR4, DRAM, SDRAM and tagged , , , , , , , , , . Bookmark the permalink.

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