Operational DDR4 SDRAM prototypes appear at ISSCC

As reported this week by several Web sites including Techeye.net, Samsung and Hynix both demonstrated working prototypes of DDR4 SDRAM at the ISSCC conference in San Francisco this week. The Samsung and Hynix DDR4 memories were manufactured in 30nm and 38nm process technologies respectively but production chips will use smaller lithographies when the memories go into volume production later this year. According to the Techeye article you can expect to see Micron, Elpida, and Nanya enter the DDR4 fray later this year as well.

For more technical information about DDR4 memories, see “The DDR4 SDRAM spec and SoC design. What do we know now?

For information on the Cadence DDR4 SDRAM controller IP block, just in case you’re working on an SoC in the server space that might need one, click here.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in DDR4, SDRAM and tagged , , , , , , , , , . Bookmark the permalink.

One Response to Operational DDR4 SDRAM prototypes appear at ISSCC

  1. Pingback: More DDR4, DDR3, and 3D IC technical details from ISSCC, courtesy of memory analyst and expert Jim Handy | Denali Memory Report

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