A new article about Wide I/O and 3D IC assembly published in EETimes brings some additional technical information to light. The article was written by Marc Greenberg and Samta Bansal, both from Cadence, and it contains both a review of successful 3D IC assembly projects to date and an overview of the advantages Wide I/O SDRAM provides to system-level designers. The successful 3D IC projects noted include the Xilinx Virtex-7 2000T FPGA—which uses a silicon interposer to consolidate four FPGA tiles into one large FPGA—and the WIOMING 3D project jointly developed by ST-Ericsson, CEA-Leti, ST Microelectronics, and Cadence Design.
I’ve called Wide I/O SDRAM, based on the JEDEC JESD229 spec, the killer app for 3D IC assembly several times and this article provides more concise technical reasons why this is so. The article states:
“With its 512-bit data interface, JESD229 Wide I/O Single Data ¬Rate (SDR) doubles the bandwidth of the Low-Power Double Data Rate 2 (LPDDR2) specification without increasing power consumption.”
It then provides this graphic, which sort of says it all:
As you can see from this graphic, Wide I/O SDRAM is a disruptive technology that really jumps performance while maintaining current power-consumption levels. This is the sort of technology that’s catnip to system designers.
Where will we see Wide I/O memory used first? Here’s what the article has to say:
“Like many new technologies, TSV has an initial cost that is higher than the technology it replaces, and simply reducing the cost of the dice in the stack may not be enough to justify its use. The ideal applications for TSV technology are those that can benefit from the dramatic improvement it brings to bandwidth, latency and power.”
For more information on the WIOMING project, see:
For more information on Wide I/O SDRAM and the JEDEC JESD229 spec, see:
For more information on the Xilinx Virtex-7 2000T FPGA, see: