Is Wide I/O SDRAM a disruptive technology? Signs say yes according to new EETimes article

A new article about Wide I/O and 3D IC assembly published in EETimes brings some additional technical information to light. The article was written by Marc Greenberg and Samta Bansal, both from Cadence, and it contains both a review of successful 3D IC assembly projects to date and an overview of the advantages Wide I/O SDRAM provides to system-level designers. The successful 3D IC projects noted include the Xilinx Virtex-7 2000T FPGA—which uses a silicon interposer to consolidate four FPGA tiles into one large FPGA—and the WIOMING 3D project jointly developed by ST-Ericsson, CEA-Leti, ST Microelectronics, and Cadence Design.

I’ve called Wide I/O SDRAM, based on the JEDEC JESD229 spec, the killer app for 3D IC assembly several times and this article provides more concise technical reasons why this is so. The article states:

“With its 512-bit data interface, JESD229 Wide I/O Single Data ¬Rate (SDR) doubles the bandwidth of the Low-Power Double Data Rate 2 (LPDDR2) specification without increasing power consumption.”

It then provides this graphic, which sort of says it all:

Low-Power DRAM Memory Bandwidth per Package, by Intro Date

As you can see from this graphic, Wide I/O SDRAM is a disruptive technology that really jumps performance while maintaining current power-consumption levels. This is the sort of technology that’s catnip to system designers.

Where will we see Wide I/O memory used first? Here’s what the article has to say:

“Like many new technologies, TSV has an initial cost that is higher than the technology it replaces, and simply reducing the cost of the dice in the stack may not be enough to justify its use. The ideal applications for TSV technology are those that can benefit from the dramatic improvement it brings to bandwidth, latency and power.”

Notes:

For more information on the WIOMING project, see:

3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say ‘Tour de Force’?

3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

For more information on Wide I/O SDRAM and the JEDEC JESD229 spec, see:

3D Week: JEDEC Wide I/O Memory spec cleared for use

3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?

3D Thursday: Boosting the bandwidth of Wide I/O SDRAM to 1 Tbit/sec through standards evolution

3D Thursday: Is Wide I/O SDRAM free for the end user???

For more information on the Xilinx Virtex-7 2000T FPGA, see:

3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!

Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)

3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)

3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology

3D Thursday: Is 2.5D IC assembly ‘buzz-worthy’?

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
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