Quickly Noted: EETimes on the challenges of testing semiconductor memory for mobile applications. Is testing really a 3D IC “stopper”?

Janine Love at EETimes interviewed Cecil Ho, President of CST (Simmtester.com)—a memory tester vendor, about issues surrounding the testing of semiconductor memory that’s optimized for and aimed at mobile applications. In these applications board real estate and physical volume are critically important, even at the expense of some additional packaging and testing cost. Consequently, you see memories in multichip packages (MCPs) where multiple DRAMs or DRAMs mixed with NAND Flash chips are all placed in one ball grid array package. To date, these memory assemblies have relied almost exclusively on wirebonding.

MCPs presents challenges for component-level testing and these challenges are often cited as “stoppers” for the evolution to 3D assembly. So I found Ho’s answer to one interview question quite interesting.

Love asked Ho:

“What kinds of tests need to be done? Why?”

Ho replied:

“Indeed, MCPs test need not be complicated. Since the DRAM and flash chips are already tested by their original vendor, only a functional test is required to detect assembly error and die handling damages.”

Using my 3D-centric eyeglasses, I’d interpret this response as clearly taking the component-level test issue out of the “stopper” category and into the “solvable” category for 3D memory-stack assembly—but maybe that’s just me.

To read the full EETimes interview with Ho, click here.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 3D, DRAM, Flash, MCP and tagged , , , . Bookmark the permalink.

One Response to Quickly Noted: EETimes on the challenges of testing semiconductor memory for mobile applications. Is testing really a 3D IC “stopper”?

  1. Pingback: test all categories | danielBpatton

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