LeCroy introduces DDR4 Bus and Timing Analyzer at DesignCon 2012

LeCroy’s Kibra 480 DDR bus and timing analyzer now lets you analyze bust traffic on DDR4 interfaces at the board and connector level. It is an evolution from the company’s earlier Kibra 380 DDR3 bus and timing analyzer. (See “How can you be sure DDR2, DDR3, and DDR4 SDRAMs will work properly in your system?”) One of the key technologies in the Kibra 480 is embodied in custom silicon that resides in a self-powered interposer board. This design approach allows the Kibra 480 analyzer to get an instant lock on the DDR4 interfaces signals so that it can capture signal traces even during power up. The analyzer can also help troubleshoot DDR3 memory subsystems with an appropriate DDR3 interposer board.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in DDR3, DDR4, DRAM, SDRAM and tagged , , . Bookmark the permalink.

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