LeCroy’s Kibra 480 DDR bus and timing analyzer now lets you analyze bust traffic on DDR4 interfaces at the board and connector level. It is an evolution from the company’s earlier Kibra 380 DDR3 bus and timing analyzer. (See “How can you be sure DDR2, DDR3, and DDR4 SDRAMs will work properly in your system?”) One of the key technologies in the Kibra 480 is embodied in custom silicon that resides in a self-powered interposer board. This design approach allows the Kibra 480 analyzer to get an instant lock on the DDR4 interfaces signals so that it can capture signal traces even during power up. The analyzer can also help troubleshoot DDR3 memory subsystems with an appropriate DDR3 interposer board.
Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
What's hot on the Denali Memory Report?
- Compact Flash
- Hybrid Memory Cube
- NVM Express
- Wide I/O