Chris Ramseyer at Tweaktown was kind enough to notice and snap this photo of Micron’s incredible shrinking Flash memory chips at this week’s Storage Visions event in Las Vegas. The image shows graphically what the numbers tell us intellectually. Starting with 50nm chips, Micron has halved the number of chips needed to store 16Gbytes of information starting in 2006 with eight 16Gbit MLC (multi-level cell) chips. The 34nm node gave us 32Gbit devices; the 25nm node delivered 64Gbit devices; and now the 20nm node is delivering 128Gbit devices. The amount of silicon needed to store 1Gbyte has dropped during this period from 87 to less than 13 mm2.
Denali Memory Report:
The Denali Memory Report is produced by Cadence Design Systems, Inc. It delivers memory market news, discussions of market trends, products and product strategies of the memory vendors, plus information about alliances and industry consortia.
- Some great analysis on SSD wear leveling and power consumption
- The Economist covers PCM – must be something real
- Add OCZ to the growing list of SSD vendors differentiating their drives with a proprietary controller
- IDT announces DDR4 register chip for DDR4 registered DIMMs and 3D die stacks
- Western Digital sampling 5mm, 2.5-inch, 500Gbyte hybrid HDD with NAND Flash
What's hot on the Denali Memory Report?
- Compact Flash
- Hybrid Memory Cube
- NVM Express
- Wide I/O