The ONFI 3.0 specification—released in March, 2011—raises the bar on the interface to Flash semiconductor memory. In particular, it boosts transfer rates to 400 Mtransfers/sec using an NV-DDR2 DDR-400 signaling protocol; it adopts 1.8V SSTL_18 differential signaling on the strobes to boost speed and cut power consumption; and it supports on-die termination (new for the 3.0 version of the ONFI spec). Key semiconductor memory suppliers with their names on the ONFI 3.0 specification include Hynix, Intel, Micron, SanDisk, and Spansion. (Note: ONFI is an abbreviation of the “Open NAND Flash Interface Working Group”)
Intel and Micron jointly previewed a 128Gbit MLC (multi-level cell) NAND Flash device compatible with the ONFI 3.0 specification just last month, based on the companies’ 20nm NAND Flash process technology. As part of that introduction, the two companies revealed that they have started the production ramp on a derivative 64Gbit MLC NAND Flash device and expect a “rapid transition” to the 128Gbit device later in 2012.
So the ONFI 3.0 NAND Flash parts are on the way, which means that it’s appropriate to start incorporating ONFI 3.0 controllers and PHYs into your new SoC designs. Today, Cadence announced immediate availability of a NAND Flash controller IP block and PHY that are compatible with the ONFI 3.0 interface spec. Both the Flash controller and the PHY also support the Toggle 2.0 NAND Flash interface spec and are backward compatible with prior ONFI and Toggle interface specs. Another key feature of this IP offering is support for chip-enable interleaving, which significantly boosts performance in Flash subsystems with multiple NAND Flash devices and achieves as much as 95% of the devices’ theoretical maximum throughput. There’s yet one more piece to this puzzle. Cadence offers complementary verification IP and memory models to ease the design of SoCs using the new ONFI 3.0 interface spec.