Big week for Wide I/O: JEDEC publishes spec while Elpida ships sample 4Gbit parts

Wide I/O jumped closer to being a reality this week with two major announcements. On December 28th, Elpida announced that they were making sample shipments of 4Gbit Wide-IO. (See “Let’s start the new year with a bang! Elpida ships 4Gbit Wide I/O and LPDDR3 SDRAM samples”) Today, January 5th, JEDEC announced  the publication of the Wide I/O standard, which you can download here. (Note: You may need to set up a free account first.)

The Wide I/O SDRAM interface specification is a revolutionary new memory interface technology using a wide array of 512 data pins to connect an SoC to a DRAM and achieves a huge peak bandwidth (more than 100Gbits/sec) using a relatively low 200MHz clock rate (single data rate). Current generation LPDDR2 SDRAM interface technology, by comparison, delivers a peak bandwidth of 34Gbits/sec per die, so the Wide I/O spec delivers roughly three times the memory bandwidth compared with the fastest current LPDDR2 devices. Elpida says that their Wide I/O SDRAM design “…results in approximately 50% less power consumption compared with DDR2 Mobile RAM (LPDDR2), currently the leading DRAM choice for mobile devices, configured at the same transfer rate.”

Wide I/O technology relies on Through Silicon Vias (TSVs), a relatively new 3D IC technology that creates thousands of connections between two die stacked together using vias and solder microbumps to connect the die (3D chip-to-chip stacking). Alternatively, two memory die can be joined with a silicon interposer where the silicon interposer incorporates the TSVs (called the “2.5D” silicon interposer method). Cadence offers design tools and a test methodology for 2.5D and 3D assembly in addition to a Wide I/O SDRAM controller and PHY IP to help you incorporate the Wide I/O interface technology into your next SoC design.

Today’s JEDEC announcement is exciting news for Cadence. We have been investing in Wide I/O technology from an early stage and participating in the JEDEC standardization process. Cadence announced the industry’s first Wide-IO Controller IP solution in March 2011 and then announced our collaboration in producing Wide I/O test chips with ST-Ericsson and CEA-LETI.

For more information on that project, see “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say ‘Tour de Force’?

–Marc Greenberg

Advertisements

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in JEDEC, LPDDR2, SDRAM, Wide I/O and tagged , , , , , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s