For more technical information about DDR4 memories, see “The DDR4 SDRAM spec and SoC design. What do we know now?”

For information on the Cadence DDR4 SDRAM controller IP block, just in case you’re working on an SoC in the server space that might need one, click here.

Enterprise-class storage requires more data reliability under harder use than consumer-grade NAND Flash is designed to accommodate, so making a high-grade SSD from lesser-grade NAND Flash is an interesting exercise in system development. As the Computerworld article says, consumer-grade MLC NAND Flash chips are rated for perhaps 3000 program/erase cycles and that sort of raw endurance would be fatal for an enterprise-class SSD. The new Optimus Ultra SSD from SMART Storage  has an endurance rating of 100,000 program/erase cycles, so something pretty interesting is going on inside of the box.

The Computerworld article say this about the way SMART Storage boosts drive endurance:

“SMART Storage achieves its NAND flash endurance through a combination of aggregated flash management and signal processing techniques. Aggregated flash management combines writes to reduce wear and signal processing increases the signal-to-noise ratio, making it possible to continue reading data even as electrical interference rises as electrons leak between flash cells.”

Uh huh.

Write combining to reduce the number of write-erase cycles is a well-known technique. Any good SSD controller should be able to support that, although there are clever ways to do it and then there are ways that are even more clever. However, what’s this stuff about signal processing? How do you get at the information needed to evaluate cells inside of a NAND Flash device?

I checked with the SMART Storage Web site to seek more illumination and found this video on the Company’s so-called Guardian Technology:

And then I found this article on the StorageReview.com site. The article explains that SMART Storage System’s Guardian Technology consists of three component technologies. The first, called FlashGuard, intelligently manages the Flash media. It maximizes the use of “stronger” Flash cells and minimizes the use of weaker cells. A key characteristic of Flash memory devices is that some cells do have less endurance and those weaker cells set the endurance spec for the entire Flash chip if all of the on-chip cells are treated equally. SMART Storage has figured out how to detect, map, and isolate these weaker cells at manufacturing time to increase system endurance. FlashGuard also employs a proprietary ECC algorithm to further boost data integrity.

The second endurance-boosting component technology in the Guardian triad is called DataGuard, which combines data-path protection, ANSI T10 DIF (data integrity field) protection blocks (just like the big boys use), and cross-die redundancy.

The third component technology is called EverGuard, which appears to be an internal power-backup technology based on capacitive energy storage, coupled with some architectural features that manage internal drive power more effectively to ensure that scheduled writes can occur even when system power is lost.

Together, these technologies telegraph a truth in the SSD market. It’s not going to be possible to just slap an SSD together using standard NAND Flash memories, an off-the-shelf controller chip, and some vendor’s standard SSD firmware and hope to compete for high-margin opportunities. SMART Storage has obviously put a lot of thought into the design of the Optimus Ultra SSD to make it stand out in a market that becomes more crowded by the day.

How will your SSD development team do the same?

I’ve called Wide I/O SDRAM, based on the JEDEC JESD229 spec, the killer app for 3D IC assembly several times and this article provides more concise technical reasons why this is so. The article states:

“With its 512-bit data interface, JESD229 Wide I/O Single Data ¬Rate (SDR) doubles the bandwidth of the Low-Power Double Data Rate 2 (LPDDR2) specification without increasing power consumption.”

It then provides this graphic, which sort of says it all:

Low-Power DRAM Memory Bandwidth per Package, by Intro Date

As you can see from this graphic, Wide I/O SDRAM is a disruptive technology that really jumps performance while maintaining current power-consumption levels. This is the sort of technology that’s catnip to system designers.

Where will we see Wide I/O memory used first? Here’s what the article has to say:

“Like many new technologies, TSV has an initial cost that is higher than the technology it replaces, and simply reducing the cost of the dice in the stack may not be enough to justify its use. The ideal applications for TSV technology are those that can benefit from the dramatic improvement it brings to bandwidth, latency and power.”

Notes:

For more information on the WIOMING project, see:

“3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say ‘Tour de Force’?”

“3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work”

For more information on Wide I/O SDRAM and the JEDEC JESD229 spec, see:

“3D Week: JEDEC Wide I/O Memory spec cleared for use”

“3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?”

“3D Thursday: Boosting the bandwidth of Wide I/O SDRAM to 1 Tbit/sec through standards evolution”

“3D Thursday: Is Wide I/O SDRAM free for the end user???”

For more information on the Xilinx Virtex-7 2000T FPGA, see:

“3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!”

“Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)”

“3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)”

“3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology”

“3D Thursday: Is 2.5D IC assembly ‘buzz-worthy’?”

NAND Flash memory makers optimize for volume and the volume driver for NAND Flash at the moment is USB memory drives. These USB drives completely replaced floppy disks about a decade ago and, consequently, NAND Flash memory chips have some very specific characteristics peculiar to removable media.

8-inch, 5.25-inch, and 3.5-inch Floppy Disk Drives

The important figures of merit for Flash-based USB drives are capacity and price/bit. Further, these solid-state USB drives are not written often. They serve as backup and data-transfer devices. Because of these figures of merit, NAND Flash vendors have been pushing capacity and cost/bit at the expense of other parameters. NAND Flash vendors ride the scaling curve of Moore’s Law as hard as they can, with 25nm and “20nm-class” commercial devices now in production. NAND Flash manufacturing is way ahead of production DRAM and logic lithographies. At the same time, NAND Flash vendors have started to pack two or more bits into each logic cell using the inherent analog nature of the NAND Flash charge-storage mechanism to correlate the amount of stored charge with a mutlibit value.

As a result of these optimizations, several important characteristics of NAND Flash memories degrade as bit density and cost/bit improve. In particular, performance (read/write speed) and reliability suffer. Taking these trends to an extrapolated conclusion, the authors write “…it will be extremely difficult to design SSDs that reduce cost per bit without becoming too slow or too unreliable (or both) as to be unusable in enterprise settings. We conclude that the cost per bit for enterprise-class SSDs targeting general-purpose applications will stagnate.”

Grim news indeed.

Or is it? After all, it’s only a prediction, so far.

Popular online summaries of this paper dwell on the inevitable winding down of SSDs in the future—perhaps over the next ten or twelve years. But before we start to run around like Chicken Little and proclaim that the sky is falling, let’s take a look at the assumptions the authors have made because they exert a significant bias to the conclusions. Perhaps things are not as bleak as the paper’s title might have us believe.

One of the key elements used to create the paper’s dire forecast is the creation of a formal model of an SSD called the “SSD-CDC” or “SSD with a constant die count.” Here’s the reasoning: Current commercial SSD controller chip architectures implement 24 NAND Flash control channels with each channel handling a maximum of four NAND Flash die. So the SSD-CDC can accommodate no more than 96 NAND Flash memory die. The “SSD-CDC’s architecture is representative of high-end SSDs from companies such as FusionIO, OCZ and Virident,” write the authors.

The 96-die limitation is an important limiting assumption in this paper. Given a physical limitation with respect to die count per SSD, the only way to increase drive capacity is to increase die capacity. You can ride Moore’s Law just so far and in this paper the authors ride Moore’s Law all the way to 6.5nm process geometries from a 34nm baseline.

Another capacity dimension is the number of bits stored in each  NAND Flash memory cell. The authors ride the bit/cell dimension to three (three-layer cell (TLC) NAND Flash die). With the number of die limited to 96 and the number of bits/cell limited to three, the authors hit a 14Tbyte ceiling for SSD capacity when the geometries hit 6.5nm.

Well, 14Tbytes isn’t a bad capacity, at least not today, but it’s the latency and bandwidth limitations that worry the authors more. They write, “Reaching beyond 4.6 TB pushes write latency to 1 ms for MLC-2 and over 2.1 ms for TLC. Read latency, rises to least 70 μs for MLC-2 and 100 μs for TLC… Either SSD-CDC’s capacity stops scaling at ~4.6 TB or its read and write latency increases sharply because increasing drive capacity with fixed die area would necessitate switching cell technology from SLC-1 or MLC-1 to MLC-2 or TLC-3… SSDs offer moderate gains in bandwidth relative to disks, but very large improvements in random IOP performance. However, increases in operation latency will drive down IOPs and bandwidth.”

Do you believe this? Is it true?

Given the authors’ assumptions, it might well be true, if all factors stay constant.

However, all factors are not constant no matter what kind of technology you’re talking about.

Perhaps the biggest factors to discuss here—although not the only ones—are 3D IC assembly and 3D IC manufacturing. First, the NAND Flash vendors know they are in a situation of diminishing returns and have started to seriously consider 3D IC manufacturing to allow a Z dimension in the construction of individual NAND Flash memory cells. (See “3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron” and “The End of NAND Flash as we Know It: Micron’s Dean Klein and Samsung’s Tony Kim Look at Life After Flash”)

Micron 3D NAND Flash Memory Cell

Multi-level and triple-level NAND Flash cells are not the only way to skin the cat, so to speak, and 3D IC manufacturing could revolutionize NAND Flash manufacture as early as next year. Micron, Samsung, and Toshiba have all discussed 3D NAND Flash cell architectures at public events. The onset of 3D NAND Flash memory cells will certainly affect some of the latency and bandwidth assumptions in the “Bleak Future” paper.

Next, consider 3D IC assembly. The notion of limiting each NAND Flash controller channel to four die is based, in part, on a pcb real-estate calculation that doesn’t take 3D IC assembly into account. You can save a lot of real estate using 3D IC assembly techniques so the assumed 4-die/channel limitation might therefore fall by the wayside.

You could also call into question the 24-channel limitation itself. Again, more reliance on 3D IC assembly techniques might well throw the channel limitation into limbo as well. There’s nothing inherently “right” about 24 channels. It’s not even a power of two.

Finally, NAND Flash might not be the technology of the future at all for SSD storage. There are other technologies at various stages of production readiness set to challenge NAND Flash semiconductor storage. MRAM (magnetic RAM) is in early-stage production at Everspin and a handful of players including Everspin seem poised to introduce STT (spin-torque transfer) MRAM, which could well prove to be a real challenger to NAND Flash memory. (See “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit”) In addition, there’s lots of news lately about memristor and memristor-like memory, although nothing’s yet reached production. (See “HP’s memristor finds a commercial semiconductor vendor: Hynix”.) The characteristics of these new memory technologies will also alter the landscape with respect to the assumptions discussed above. There’s no law that says SSDs must be built with NAND Flash memory.

So, in short, the “Bleak Future” paper is effective in pointing out some imminent pitfalls but we don’t know how long SSDs will really last because technological disruptions prevent the smooth evolution of storage devices and stymie this sort of analysis.

Let me leave you with three lessons from memory and storage history:

1. Magnetic core memory reigned as the random-access memory of choice for 20 years—from about 1953 when the MIT Whirlwind computer became the first electronic computer to use magnetic cores through the early 1970s. Within two years of the Intel 1103 DRAM introduction in 1970, magnetic core memory production dropped off the cliff. That’s how fast a memory revolution can take place if the new replacement technology is sufficiently compelling. (Note: magnetic memory may make a comeback if commercial MRAM succeeds.)
2. The first commercially available 8-in floppy disk drive—from IBM—appeared in 1971. For decades, floppy disks regularly grew in capacity and shrank in physical volume—only to be far outpaced by size of media files, the growth in software program footprint, and the capacity increases enjoyed by hard disk drives. After three decades, the gap between floppy capacity and the immediate needs for removable storage caused the mighty floppy disk drive to fall by the wayside and solid-state USB drives got their chance to shine as NAND Flash memory technology finally came into its own—after 15 years of development.
3. The demise of hard disk drives has long been predicted. Analysts said that the rate of capacity increase for a hard disk drive was unsustainable. They were wrong. Often. Consistently. The magneticians continued to find and exploit amazing new magnetic properties so that 3.5-inch hard drives now have Tbyte capacities. Some of these amazing developments included giant magnetoresistance and PRML (Partial Response Maximum Likelihood) coding.

The lesson from these three examples is that technological revolutions are impossible to predict accurately, as are their effects.

Want to hear more about these topics? Well, Memcon 2012 is coming in September and the registration page is now open. Click here.

MRAM is one of the serious challengers to the status quo in semiconductor memory. If made commercially viable in terms of speed and density, MRAM could challenge both DRAM and NAND Flash semiconductor memory.

For more information on MRAM and STT MRAM see “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit” and “Can the Magneticians finally succeed in getting MRAM launched as a viable, low-power ASIC NV memory?”

Samsung Wide I/O SDRAM die (Definitely NOT free)

A recent email from Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, suggested that Wide I/O used in a 3D stack is free for the end user. In other words, there’s no incremental cost in the purchase price of an end product (such as a mobile phone or a tablet) that pairs Wide I/O SDRAM with a logic chip using 3D assembly techniques. Greenberg challenged me to check his math. I’m going to do just that in this blog post. See what you think.

We need to start with the incremental cost of adding TSVs (through silicon vias) to a multiprocessor SoC (MPSOC). To do that, we need to figure out much added cost there would be to add TSVs to an MPSoC die.

Well, how big is an SoC or MPSoC die that might use a Wide I/O SDRAM?

Without naming names, let’s look at a series of such SoCs from one vendor. This SoC family includes single- and multi-processor designs built with 65nm and 45nm process technology. Die sizes range from 40 to 110 mm². Marc then conjectures that a “representative” applications processor SoC measures 9x9mm, giving an area of 81mm². That’s right in the middle of the range for the existing application processor family described above.

You can fit approximately 800 such die on a 300mm wafer. (Marc provided a handy reference pointer for this computation.) Let’s suppose we get about 70% yield from this wafer (or pick your own yield number), resulting in 560 known good die per 300mm wafer.

Now all we need to do is figure out the incremental cost per wafer for adding the TSVs. Here, the numbers are all over the map. At the recent 3D Architectures for Semiconductor Integration and Packaging event held in Burlingame, California, I heard incremental cost numbers as high as $800 per wafer for adding TSVs. I’ve also read estimates of $150 (click here) and seen an estimate that the ultimate cost will be about $25 (click here) once we get the process nailed down.

What number should we use?

Let’s pick something between $150 and $800 that doesn’t require too much “hard” math. How about $560? That would make the incremental cost of adding TSVs to an SoC work out to exactly $1 per known good die. You can’t get much easier than that. If you prefer the $150 number, then it’s 27 cents per die. If you believe that eventually it will cost $25 per wafer to add TSVs, then the incremental cost is 4.5 cents per die.

In the end, you’ll see it doesn’t really matter which of those three per-die incremental costs you pick. You win in any case.

Why? Because, as Marc has been known to say, the power savings you get from using Wide I/O SDRAM permit you to shrink the battery powering the end product. You can save $1 to $3 in the battery alone from those power savings, not to mention the board-cost savings derived from reducing the IC real estate footprint when the SDRAM disappears from the board and climbs on top of the application processor.

Now, before you get all technical on me, let me acknowledge that there are a host of factors not included in this SWAG cost analysis. Neither Marc nor I compared the relative cost of compression bonding the Wide I/O SDRAM to the SoC versus wire bonding. We did not include the cost savings of entirely eliminating the packaging for the Wide I/O SDRAM nor the incremental cost of the more complex encapsulation for the 3D stack. Also, we did not factor in the cost savings resulting from the elimination of some 120 fewer pins on the SoC, which no longer needs an external SDRAM interface, and we also did not factor in the yield loss due to stack assembly.

So, is this a back-of-the-envelope calculation? You betcha! Is it a good engineering estimate for making a decision to look more seriously into 3D integration. I’d say so.

By the way, Cadence offers a Wide I/O SDRAM controller and PHY IP plus an appropriate memory model for your SoC verification efforts, just in case you feel the sudden need to design an SoC with TSVs to pair with a Wide I/O SDRAM. Feel free to check them out.

That expediency costs us in terms of lost efficiency with respect to SSDs. Take the adoption of the SATA protocol for SSDs as a case study. Where did the SATA storage protocol come from? It is a serialized version of a storage protocol called PATA or “parallel ATA.” Where did PATA come from? The “ATA” part of PATA stands for “AT Attachment” where the “AT” comes from “Advanced Technology,” which was IBM’s name for the second iteration of the original IBM PC, the IBM PC/AT. You know, the version of the IBM PC based on the “advanced” Intel 80286 processor. That PC.

Shugart Technology ST-506 Hard Disk Drive (circa 1980)

What was advanced about the ATA hard-disk interface? It moved the hard-disk controller from an expansion card into the hard drive. Please let that statement sink in. There was a time, in the pre-ATA days, when the hard disk drive was dumb as a rock. It took commands like “step in,” “step out,” “read sector,” and “write sector.” Data supplied to the disk drive had to be appropriately encoded by the external hard-disk controller. This even older, more primitive hard-disk interface came from the original Shugart Technology 5Mbyte (as in “megabyte”) ST-506, the original 5.25-inch hard drive introduced in 1980. Everyone in the hard disk industry—eventually hundreds of vendors—quickly copied the ST-506 interface.

The innovation of the ATA interface—originally developed by Western Digital as the IDE (Integrated Drive Electronics) interface—was to make the hard-disk controller more intimate with the hard drive and the HDA (head disk assembly). This move freed the controller from needing to know how to best control every hard disk ever made. An IDE controller only needs to know about the HDA that it’s welded to.

Because of all this legacy, the SATA protocol still needs to know the basics of hard-disk management. The protocol keeps track of cylinders, heads, and sectors—the atoms and molecules of hard-disk-based storage.. These concepts, of course, are only associated with spinning media—hard-disk storage. They have no meaning for storage based on NAND Flash semiconductor memory. To be used with NAND Flash media, these concepts must first be translated.

Now let’s step back and take a breath here. Let’s remember what we’re actually trying to do at the highest level. At the application level, we actually deal with files. Not cylinders. Not heads. Not sectors. However, the hard disk drive has become so integral to microprocessor-based computing over the past three decades (since the ST-506 drive appeared in 1980) that the translation from files to cylinders, heads, and sectors is buried deeply into our operating systems. With no alternatives for storage, it made perfect sense to meld the file-storage needs of the operating system with the sector-centric world view of the hard disk.

NAND Flash memory does not share that world view.

And that is what brings us (taking the long way home) to NVMe or NVM Express. Leading companies in the storage industry have recognized that the current, popular storage interfaces are too hard-disk centric; they carry too much conceptual baggage that caters to the specific needs of hard disk drives since 1980. Now this baggage is old, but it still serves us well as long as we’re using hard drives. It doesn’t work as well for SSDs. The following diagram shows why.

The block diagram shows the number of translation steps needed to get from the Host CPU to storage in the NAND Flash memory cells. The Host CPU’s parallel bus is serialized and transformed into PCIe, currently the leading bus interface for PCs and many servers. Somewhere, perhaps on a motherboard or perhaps on an expansion card, the PCIe interface is transformed into a SATA interface. The SATA interface then arrives at a SATA controller that manages the attached “hard drives,” whether these drives are actually hard disk drives or SSDs.

At some point, the SATA commands (cylinders, heads, sectors) must be transformed into storage blocks more readily understood by the NAND Flash memories. The NAND Flash memories have their own special needs or peculiarities such as their own block/bank/sectoring scheme, error management protocols including ECC, and wear-leveling algorithms. These peculiarities are handled by the NAND Flash Controller, which then drives the attached NAND Flash memory devices as appropriate.

Translation from PCIe to SATA then to NAND Flash results in a lot of unnecessary overhead, brought on by the desire to slip SSDs into the supply chain with as little disruption as possible.

However, the industry now seems ready to trade off some disruption for more efficiency. The NVMe standard is the result of that change in mindset. Using the NVMe approach, an SSD-based system might look something like this:

To get to this point, changes must occur deep in the operating system. The NVMe specification is now getting close to a year old. Windows and Linux drivers now exist. The revolution is coming.

For more information on the NVMe specification, click here.

1. Speed: “…in the second half of 2012, mass adoption of SSDs will reach a tipping point. He says last year saw a steady increase in SSD sales, adding that the increased interest was primarily newly ‘tech-savvy’ consumers and not only tech enthusiasts. The value of adding an SSD to a lagging computer is now in the thoughts of many mainstream consumers.”In other words, a wide swath of computer users and other consumers have tasted the performance benefits of NAND Flash storage and they’re not going back. Consequently, you must now divine the best approach for melding NAND Flash storage into all manner of designs or face the sales consequences to be “earned” from relatively sluggish performance across all consumer, computer, and communications end products.
2. Capacity: “worldwide sales of tablets are predicted to jump to 326.3 million units by the end of 2015… the high-quality content being consumed on mobile devices will continue to drive storage demand. Consumers who have tablets that do not feature card slots for extended storage are already experiencing storage limitations.”This is actually an old lesson made new by SSDs: there’s no such a thing as too much storage. Video, image, and audio files will grow to fill whatever’s available. Be sure to incorporate some sort of expansion facility into every product to meet customer needs and to pick more dollars up from the table.
3. Cloud: “… SSDs will gain traction in the data centre market. This market segment has built enough trust in SSD technology to consider the replacement of existing HDDs… High input-output operations per second (IOPs) results means that SSDs are far more suitable for the server environment than HDDs… the push to increase energy savings and optimize performance computing will see SSDs become a priority investment for data centers in 2012.”In other words, the cloud is where it’s at for many large application zones and SSDs give clouds more performance. Time is money.