Category Archives: Wide I/O

See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video

This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading

Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, LPDDR3, Wide I/O | Tagged , , , | Leave a comment

3D Thursday: Advantest 3D tester produces known good die and known good stacks

3D can’t move forward until the testability issues are solved. Hear that one? Well, Advantest has just advanced another click in that ratchet with this week’s introduction of a concept model test cell for TSV-based 2.5D and 3D products. It’s … Continue reading

Posted in 3D, Wide I/O | Tagged , , , | Leave a comment

Invensas to detail POP interconnect to rival Wide I/O with as many as 1200 interconnections between IC packages

Later this week, Invensas will detail its new BVA (bond via array) package-on-package (POP) interconnect that can achieve 1200 electrical connections between chip packages without the use of 3D die assembly. Information on the technology will be contained in a … Continue reading

Posted in 3D, Wide I/O | Tagged , , , | Leave a comment

Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products… we need low-cost 3D IC assembly”

Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including … Continue reading

Posted in 3D, DRAM, SDRAM, Wide I/O | Tagged , , , , | 1 Comment

Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?

Multicore SoC and processor designs were our solution to the death of Dennard Scaling when IC process geometries dropped below 90nm, when processor speeds hit 3GHz, and when processor power consumption went off the charts. Since 2004, we’ve transformed Moore’s … Continue reading

Posted in 3D, DDR, DDR3, DDR4, DRAM, Flash, PCIe, Wide I/O | Tagged , , , | 9 Comments

A possible roadmap for Wide I/O that leads to 2Tbps of SDRAM memory bandwidth—per device

Cadence Product Marketing Director Marc Greenberg—one of the speakers at last week’s EDPS conference held in Monterey, California—spoke about why the Wide I/O SDRAM is probably the “killer app” that unleashes 3D IC assembly into the mainstream. Richard Goering has … Continue reading

Posted in DDR, DDR3, DDR4, DRAM, SDRAM, Wide I/O | Tagged , , , , | 2 Comments

Where does LPDDR3 SDRAM fit in the low-power memory universe? How about Wide I/O SDRAM?

Marc Greenberg, Director of Product Marketing in the Cadence SoC Realization Design IP Group, just sent me some slides in connection with the recent introduction of the Cadence design and verification IP portfolio for LPDDR3 low-power SDRAM. I’ve already written … Continue reading

Posted in DDR, DDR3, LPDDR, LPDDR2, LPDDR3, SDRAM, Wide I/O | Tagged , | 2 Comments