Category Archives: LPDDR2

How ya gonna’ control that DDR4 SDRAM next year? The 28nm answer.

Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with … Continue reading

Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, SDRAM | Tagged , , , , , , , | Leave a comment

Friday Video: A personal invitation to Memcon from Sanjay Srivastava

Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading

Posted in DDR3, DDR4, DRAM, Flash, HMC, Hybrid Memory Cube, JEDEC, LPDDR2, LPDDR3, LPDDR4, Memcon, MRAM, mSATA, NAND, NOR, NVM Express, NVMe, ONFI, PCIe, Samsung, SAS, SATA, SD, SDRAM | Tagged , , , | Leave a comment

See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video

This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading

Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, LPDDR3, Wide I/O | Tagged , , , | Leave a comment

Want more details about the new Micron 1Gbit Phase-Change Memory / 512Mbit SDRAM device? Here are several

Yesterday, Micron announced volume production of a new memory device containing one 1Gbit PCM (phase-change memory) die and one 512Mbit LPDDR2 SDRAM die. This morning, I had a conversation about this new device with Philippe Berge—Senior Director of the NOR, … Continue reading

Posted in DDR, Flash, LPDDR2, Micron, NOR, PCM, Storage | Tagged , , , , , , , | Leave a comment

Micron announces volume production of PCM/DRAM multichip packaged memory

Totally not expecting this. Today Micron announced high-volume availability of a multichip, packaged memory device that incorporates a 1Gbit PCM (Phase-Change Memory) and a 512Mbit LPDDR2 SDRAM. The PCM die is built with 45nm process technology. The multichip-packaged memory is … Continue reading

Posted in DRAM, LPDDR2, Micron, PCM, SDRAM | Tagged , , , | 1 Comment

Want a quick and dirty overview of the new JEDEC LPDDR3 spec? EETimes serves it up

Kristin Lewotsky has just published an LPDDR3 SDRAM interview with Huong Vuong, Chairman of the JEDEC JC-42.6 Subcommittee for Low Power Memories. Here are the salient points from the interview, in my opinion: The purpose of LPDDR3 is to increase … Continue reading

Posted in LPDDR2, LPDDR3, LPDDR3E, LPDDR4, SDRAM | Tagged , , , , , , | Leave a comment

Semiconductor memory plays a large role in smartphone design says Matti Floman of Nokia

“There’s no real difference between PCs and mobile phones today,” said Matti Floman from Nokia who gave the first keynote speech at last week’s JEDEC Mobile Forum. There is no difference in the types of applications run; there’s no difference … Continue reading

Posted in 3D, DDR, LPDDR2, Memristor, MRAM, SDRAM, Storage, UFS | Tagged , , , , , | Leave a comment