Category Archives: DRAM

Test your system design for DDR4 JEDEC compliance with this $4500 ‘Scope add-on

Agilent has just announced a compliance test application for DDR4 SDRAM system designs. The $4500 Agilent N6462A DDR4 test application accelerates bring-up and debugging of DDR4 SDRAM-based systems by automating a bevy of physical-layer I/O testing with the company’s 9000 … Continue reading

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Save the date: JEDEC DDR4 Workshop, Santa Clara, CA. October 30-31

JEDEC is sponsoring a 2-day DDR4 workshop that should interest anyone planning on using DDR4 SDRAM in next-generation designs. Day 1: DDR4 vs DDR3: Comparison Matrix Why migrate to DDR4 Power-on, initialization, and training Read/Write and refresh operation review Day … Continue reading

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See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video

This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading

Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, LPDDR3, Wide I/O | Tagged , , , | Leave a comment

How many DRAMs does it take to populate a supercomputer? 746,496 plus a lot of hot water for cooling

Jim Handy, The Memory Guy, posted a short blog about the 3-petaFLOP (peak) SuperMUC supercomputer at the Leibniz Supercomputing Centre on the outskirts of Munich, Germany. (The “MUC” in SuperMUC is the 3-letter code for the Munich airport. Now that’s … Continue reading

Posted in DDR3, DRAM, Samsung, SDRAM | Tagged , , , , , , , | 1 Comment

Who do you want to see at Memcon?

As the emcee for the Memcon event on September 18, I’ve been given the opportunity to personally invite a few, select exhibitors to the show and to cut them a very sweet deal. To do that, I’d like to know … Continue reading

Posted in DDR, DRAM, Flash, MRAM, NAND, SSD | Tagged , , , , , , , | Leave a comment

Micron announces volume production of PCM/DRAM multichip packaged memory

Totally not expecting this. Today Micron announced high-volume availability of a multichip, packaged memory device that incorporates a 1Gbit PCM (Phase-Change Memory) and a 512Mbit LPDDR2 SDRAM. The PCM die is built with 45nm process technology. The multichip-packaged memory is … Continue reading

Posted in DRAM, LPDDR2, Micron, PCM, SDRAM | Tagged , , , | 1 Comment

Want another opinion about the Hybrid Memory Cube? Michael Feldman of HPCwire.com weighs in

Michael Feldman over at HPCwire.com has just published his own analysis of the Hybrid Memory Cube (HMC), which I’ve covered extensively in the EDA360 Insider and the Denali Memory Report (see below). Feldman reiterates many of the same points I’ve … Continue reading

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