Category Archives: DDR3

How ya gonna’ control that DDR4 SDRAM next year? The 28nm answer.

Cadence has just completed testing of its DDR4 SDRAM controller and PHY in two of the TSMC 28nm process technologies: 28HPM and 28HP. The DDR4 PHY exceeds the data rates needed to operate DDR-2400 SDRAMs and it is interoperable with … Continue reading

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Friday Video: A personal invitation to Memcon from Sanjay Srivastava

Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading

Posted in DDR3, DDR4, DRAM, Flash, HMC, Hybrid Memory Cube, JEDEC, LPDDR2, LPDDR3, LPDDR4, Memcon, MRAM, mSATA, NAND, NOR, NVM Express, NVMe, ONFI, PCIe, Samsung, SAS, SATA, SD, SDRAM | Tagged , , , | Leave a comment

See the future of DRAM usage, at least until 2015. Marc Greenberg from Cadence lays it out in a video

This year at DAC, Marc Greenberg gave a presentation on the near- and medium-term future of DRAM in the ChipEstimate booth. Two separate technology paths will dominate: the PC/server space and the mobile space. By 2015, PCs and servers will … Continue reading

Posted in DDR, DDR3, DDR4, DRAM, LPDDR2, LPDDR3, Wide I/O | Tagged , , , | Leave a comment

How many DRAMs does it take to populate a supercomputer? 746,496 plus a lot of hot water for cooling

Jim Handy, The Memory Guy, posted a short blog about the 3-petaFLOP (peak) SuperMUC supercomputer at the Leibniz Supercomputing Centre on the outskirts of Munich, Germany. (The “MUC” in SuperMUC is the 3-letter code for the Munich airport. Now that’s … Continue reading

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Samsung’s 20nm-class DDR3 SDRAM runs on 1.35V, saves 2/3 of the power used by 50nm-class, 1.5V SDRAM

Not all DDR3 SDRAM is created equal. That’s the message Samsung is spreading lately by talking about its 20nm-class DDR3 SDRAM. The company is using 1.5V, 50nm-class DDR3 SDRAM as a benchmark and says that a server loaded with 96Mbytes … Continue reading

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Designing circuit boards with DDR3? Full-day, hands-on tutorial in Europe shows you how. Munich, May 14

System designs employing DDR3 SDRAMs present many new pcb design challenges compared to DDR2. DDR3 clock, address, and control lines employ a new fly-by topology; setup and hold times need to be just right because there are reduced timing margins … Continue reading

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Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?

Multicore SoC and processor designs were our solution to the death of Dennard Scaling when IC process geometries dropped below 90nm, when processor speeds hit 3GHz, and when processor power consumption went off the charts. Since 2004, we’ve transformed Moore’s … Continue reading

Posted in 3D, DDR, DDR3, DDR4, DRAM, Flash, PCIe, Wide I/O | Tagged , , , | 9 Comments