Want some additional details about the Micron Hybrid Memory Cube?

This week at Design West (the conference previously known as the Embedded Systems Conference), I had a chance to speak with Mike Black from Micron about the Hybrid Memory Cube (HMC), a 3D DRAM assembly aimed at high-performance computing. The first thing he told me was that Micron had built an operational prototype of the HMC. It delivers 121Gbytes/sec of bandwidth, about 95% of the target bandwidth: 128Gbytes/sec. He promised to send me a photo, but it looks like a prototype not a finished product so Micron has not been eager to pass the image around.

The HMC is based on a 5-die 3D stack. The top four die are DRAM (not SDRAM) die with the old RAS/CAS sort of arrangement. That’s so that Micron can build these DRAMs to run at the native RAM arrays speed. All of the DRAM control and I/O protocols are embodied in the bottom die, the fifth die, that’s currently made by HMC Consortium member IBM.

Black expects the first samples of HMC assemblies to appear in the first half of 2013. Based on DRAM litho roadmaps, he expects each of the DRAM die to have 4Gbit capacities by then. With four die, that means the sample HMCs in mid 2013 will have 16Gbit or 2Gbyte storage capacities. By 2015, Black expects that capacity to double as the DRAM chips reach 8Gbits per die.

The next step is to consider the link between the HMC and the host system. Currently this link is implemented as multiple high-speed differential serial channels. In the future, it might be an optical connection, which reminded me of the recently announced optical FPGA from Altera. That FPGA uses two 150Gbps MicroPOD optical transceivers from Avago for communications. After my meeting with Black, I went back into the Design West exhibit area where Altera was demonstrating that same optical FPGA. The Avago MicroPOD optical transceivers consume 2 or 3 Watts and can transmit signals for more than a few meters. (For more information, see “3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet”)

For more information about the HMC, see:

Note: Micron is presenting at the Electronic Process Design Symposium (EDPS) next week, on April 6. You now have less than a week to sign up for this event and if you have any interest in 3D IC assembly, then you need to be in Monterey on April 6.

More information about EDPS here.

Register for EDPS here.

About these ads

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 3D, DRAM, HMC, Hybrid Memory Cube and tagged , , , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s