Yesterday, DRAMeXchange published some performance tests on five 120Gbyte SSDs. The results may surprise you. Click here:
DRAMeXchange’s 2012 SSD Ranking – 120 GB SSD (SATA 2)
Yesterday, DRAMeXchange published some performance tests on five 120Gbyte SSDs. The results may surprise you. Click here:
DRAMeXchange’s 2012 SSD Ranking – 120 GB SSD (SATA 2)
Several sources including TomsHardware.com have reported the appearance at the 15th Embedded Systems Expo in Japan of an SSD built by Buffalo Memory Company with MRAM for cache memory. The drive uses 8Mbytes of MRAM (magnetic RAM) as a cache for the much larger Flash storage array and the nonvolatile nature of the MRAM gives the drive more protection from power loss. All of the articles about this product suggest that the drive has an overall capacity of 4Gbytes, but that seems unlikely in a new product considering the state of Flash manufacturing and the sizes of competing SSDs. We’ll have to wait to see what the final drive looks like because Buffalo has not yet announced the product formally.
In case you need an SSD that can be wiped quickly, RunCore has introduced the InVincible SSD with two modes of erasure: non-destructive and destructive. Two buttons—one red, one green—activate the erasure. The two buttons apparently connect to the SSD’s normal SATA drive connector. The green button simply erases the drive’s internal Flash memory. For really sensitive data, the red button applies excessive voltage to the Flash memory letting out the magic smoke (seen in the video below) and this preventing the drive from ever working again.
Here’s the video:
Postscript: the SSD on my laptop failed catastrophically just yesterday. Maybe I shouldn’t have written up this particular story for the Denali Memory Report.
Earlier this month, JEDEC published the LPDDR3 specification for the next generation of low-power SDRAM that will be used in mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks. The LPDDR3 supports memory transfer rates of 6.4Gbits/sec—12.8Gbits/sec for a dual-channel configuration—and the DDR4 spec support memory transfer rates of 3.2Gbits/sec per pin. Now, the DDR PHY Interface (DFI) Group has announced a revision of the DFI specification (version 3.1) that adds LPDDR3 and DDR4 capabilities to the existing specification. The DFI spec defines a standard interface between DDR memory controllers and the PHYs that communicate directly with the associated SDRAM chips.
Coincident with the DFI announcement, Cadence has announced DDR controller and DDR PHY design IP and verification IP that conforms to the DFI and JEDEC specifications.
Later this week, Invensas will detail its new BVA (bond via array) package-on-package (POP) interconnect that can achieve 1200 electrical connections between chip packages without the use of 3D die assembly. Information on the technology will be contained in a paper titled “Fine Pitch Copper PoP for Mobile Applications” to be given during the 3D Technology session (June 1) at the Electronic Components and Technology Conference (ECTC) at the Sheraton San Diego Hotel and Marina in San Diego.
The Invensas press release claims that the company’s BVA technology permits as many as 1200 interconnections between packages using conventional POP assembly techniques using an interconnect pitch as small as 0.2mm. Because it is a POP technology, Invensas also claims that its BVA technology extends the life of the existing package assembly and SMT infrastructure.
“There’s no real difference between PCs and mobile phones today,” said Matti Floman from Nokia who gave the first keynote speech at last week’s JEDEC Mobile Forum. There is no difference in the types of applications run; there’s no difference in performance; there’s no difference in connectivity. Because smartphones now offer the sort of universal, run-any-app abilities of PCs, they are rapidly moving down the phone hierarchy, penetrating the broad mobile phone subscriber market and pushing out phones with lesser abilities such as feature phones.
Although user expectations are not different between PCs and phones, there’s certainly a difference in terms of hardware design. It’s not easy to make powerful memory that doesn’t consume lots of power, said Floman. In addition, phones need to fit more and more memory capacity into smaller and smaller volumes to make room for more battery in the phone—to accommodate users’ desire for more time between battery charges. Smartphone form factors are also evolving, said Floman. The favored form factor these days is a thin phone with a large display.
Semiconductor memory requirements to accommodate these design characteristics include:
Then Floman focused on what’s really important now: power. “Power is the focus of the future,” he said. Power consumption is limited by battery capacity and the heat tolerance of stacked packages, because whether or not the mobile phone makers are using 3D IC assembly, they are already stacking die. Here’s an image Floman used to show the evolution of 3D stacking in smartphone design.
Floman noted that the maximum operating temperature for NAND Flash devices is 85° C and that DRAMs are limited to 105° C. Die stacking compounds the problem of heat dissipation.
One of the most interesting slides that Floman presented at the JEDEC Mobile Forum, in my opinion, was an image that showed three processor/memory architectures for mobile phones. The graphic looked like this:
The two architectures on the left are execute-in-place (XIP) architectures. The leftmost architecture employs pseudo-static RAM and NOR Flash as memory and executes operating-system code directly from the NOR Flash memory. The middle architecture replaces the pseudo-static RAM and NOR Flash memory with LPDDR2 SDRAM and LPDDR2-N Non-Volatile Flash memory. It’s still an execute-in-place architecture but the memory components are newer and deliver more performance with better capacity.
The architecture on the right is a shadowing architecture where the OS code is stored in a mass-storage device (NAND Flash memory) and the code is first transferred to DRAM and then executed. High-end smartphones use this architecture.
These architectural designs will hold unless a new type of memory with both fast read/write times and non-volatile storage become commercially available in the required capacities and the required cost per bit. If that happens, the smartphone will only need one memory type—perhaps that might be magnetic RAM (MRAM) or Memristor-based memory. But that’s not the situation today.
The best possible performance, said Floman, will come from Wide I/O DRAM while the UFS (Universal Flash Storage) standard appears to be poised to become the next commonly used storage medium for smartphone design. UFS “will be the next generation mass memory” for smartphones, said Floman.
All of this evolution has but a single purpose. “You will not buy your next phone from the same manufacturer unless it provides new functions,” Floman said as he concluded his keynote speech.